<?xml version="1.0" encoding="ISO-8859-1"?><article xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<front>
<journal-meta>
<journal-id>1665-6423</journal-id>
<journal-title><![CDATA[Journal of applied research and technology]]></journal-title>
<abbrev-journal-title><![CDATA[J. appl. res. technol]]></abbrev-journal-title>
<issn>1665-6423</issn>
<publisher>
<publisher-name><![CDATA[Universidad Nacional Autónoma de México, Instituto de Ciencias Aplicadas y Tecnología]]></publisher-name>
</publisher>
</journal-meta>
<article-meta>
<article-id>S1665-64232004000300002</article-id>
<title-group>
<article-title xml:lang="en"><![CDATA[Flow control design for a flexible and adaptive router in parallel systems]]></article-title>
</title-group>
<contrib-group>
<contrib contrib-type="author">
<name>
<surname><![CDATA[De Luca]]></surname>
<given-names><![CDATA[A.]]></given-names>
</name>
<xref ref-type="aff" rid="A01"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Jiménez]]></surname>
<given-names><![CDATA[A.]]></given-names>
</name>
<xref ref-type="aff" rid="A02"/>
<xref ref-type="aff" rid="A03"/>
</contrib>
</contrib-group>
<aff id="A01">
<institution><![CDATA[,Instituto Politécnico Nacional Centro de Investigación y de Estudios Avanzados Ingeniería Eléctrica]]></institution>
<addr-line><![CDATA[México Distrito Federal]]></addr-line>
<country>México</country>
</aff>
<aff id="A02">
<institution><![CDATA[,Universidad Autónoma Metropolitana Departamento de Electrónica ]]></institution>
<addr-line><![CDATA[Azcapotzalco Distrito Federal]]></addr-line>
<country>México</country>
</aff>
<aff id="A03">
<institution><![CDATA[,Instituto Politécnico Nacional Escuela Superior de Ingeniería Mecánica y Eléctrica Departamento de Ingeniería Eléctrica]]></institution>
<addr-line><![CDATA[México Distrito Federal]]></addr-line>
<country>México</country>
</aff>
<pub-date pub-type="pub">
<day>00</day>
<month>00</month>
<year>2004</year>
</pub-date>
<pub-date pub-type="epub">
<day>00</day>
<month>00</month>
<year>2004</year>
</pub-date>
<volume>2</volume>
<numero>3</numero>
<fpage>199</fpage>
<lpage>204</lpage>
<copyright-statement/>
<copyright-year/>
<self-uri xlink:href="http://www.scielo.org.mx/scielo.php?script=sci_arttext&amp;pid=S1665-64232004000300002&amp;lng=en&amp;nrm=iso"></self-uri><self-uri xlink:href="http://www.scielo.org.mx/scielo.php?script=sci_abstract&amp;pid=S1665-64232004000300002&amp;lng=en&amp;nrm=iso"></self-uri><self-uri xlink:href="http://www.scielo.org.mx/scielo.php?script=sci_pdf&amp;pid=S1665-64232004000300002&amp;lng=en&amp;nrm=iso"></self-uri><abstract abstract-type="short" xml:lang="en"><p><![CDATA[The present article contains a high performance buffer design, useful for message flow control in parallel systems. The appropriate handling of the buffers is an important activity for the flow control function. The proposed buffer, which we have denominated as Self-Compacting Buffer (SCB), reduces the communication latency through a highly efficient management of their space, and a hardware implementation. The SCB was designed with a parallel-distributed control unit, using a control cell for each storage locality. Their capacity is expandable: it can grow width and length, preserving the complexity of its control cells. The SCB allows simultaneous writing and reading operations in a single clock cycle.]]></p></abstract>
<abstract abstract-type="short" xml:lang="es"><p><![CDATA[El presente artículo contiene el diseño de un buffer de alto desempeño, útil para el control de flujo de mensajes en sistemas paralelos. El manejo adecuado de buffers es una actividad importante de la función de control de flujo. El buffer propuesto, el cual hemos denominado como SCB (Buffer AutoCompactante), permite reducir la latencia de comunicación mediante una administración altamente eficiente de su espacio y una implantación de hardware. El SCB fue diseñado con una unidad de control distribuida paralela, utilizando una celda de control para cada localidad de almacenamiento. Su capacidad es expandible: puede crecer en ancho y largo, manteniendo constante la complejidad de sus celdas de control. El SCB permite la realización simultánea de operaciones de escritura y lectura en un solo ciclo de reloj.]]></p></abstract>
<kwd-group>
<kwd lng="en"><![CDATA[Routers]]></kwd>
<kwd lng="en"><![CDATA[Flow Control]]></kwd>
<kwd lng="en"><![CDATA[Parallel systems]]></kwd>
<kwd lng="en"><![CDATA[Self-compacting buffer]]></kwd>
<kwd lng="en"><![CDATA[VHDL]]></kwd>
</kwd-group>
</article-meta>
</front><body><![CDATA[  	    <p align="center"><font face="verdana" size="4"><b>Flow control design for a flexible and adaptive router in parallel systems</b></font></p>     <p align="center">&nbsp;</p>  	    <p align="center"><b><font face="verdana" size="2">A. De Luca<sup>1</sup> &amp; A. Jim&eacute;nez<sup>2,3</sup></font></b><font face="verdana" size="2"></font></p>     <p align="center">&nbsp;</p>  	    <p align="justify"><font face="verdana" size="2"><sup>1</sup>&nbsp;CINVESTAV&#45;IPN. Electric Engineering. Computation Section. e&#45;mail: <a href="mailto:dlap@delta.cs.cinvestav.mx">dlap@delta.cs.cinvestav.mx</a></font></p>  	    <p align="justify"><font face="verdana" size="2"><sup>2</sup>&nbsp;Universidad Aut&oacute;noma Metropolitana. Electronic Department. e&#45;mail: <a href="mailto:ajf@correo.azc.uam.mx">ajf@correo.azc.uam.mx</a></font></p>  	    <p align="justify"><font face="verdana" size="2"><sup>3</sup>&nbsp;ESIME&#45;IPN. Electric Engineering Department.</font></p>     <p align="justify">&nbsp;</p>  	    <p align="justify"><font face="verdana" size="2">Received: January 13<sup>h</sup>, 2003.     ]]></body>
<body><![CDATA[<br>     Accepted: April 2<sup>th</sup>, 2003.</font></p> 	    <p align="justify">&nbsp;</p> 	    <p align="justify"><font face="verdana" size="2"> <b>Abstract</b></font></p>  	    <p align="justify"><font face="verdana" size="2">The present article contains a high performance buffer design, useful for message flow control in parallel systems. The appropriate handling of the buffers is an important activity for the flow control function. The proposed buffer, which we have denominated as Self&#45;Compacting Buffer (SCB), reduces the communication latency through a highly efficient management of their space, and a hardware implementation. The SCB was designed with a parallel&#45;distributed control unit, using a control cell for each storage locality. Their capacity is expandable: it can grow width and length, preserving the complexity of its control cells. The SCB allows simultaneous writing and reading operations in a single clock cycle.</font></p> 	    <p align="justify"><font face="verdana" size="2"><b>Keywords:</b> Routers, Flow Control, Parallel systems, Self&#45;compacting buffer, VHDL.</font></p>     <p align="justify">&nbsp;</p>  	    <p align="justify"><font face="verdana" size="2"><b>Resumen</b></font></p>  	    <p align="justify"><font face="verdana" size="2">El presente art&iacute;culo contiene el dise&ntilde;o de un buffer de alto desempe&ntilde;o, &uacute;til para el control de flujo de mensajes en sistemas paralelos. El manejo adecuado de buffers es una actividad importante de la funci&oacute;n de control de flujo. El buffer propuesto, el cual hemos denominado como SCB (Buffer AutoCompactante), permite reducir la latencia de comunicaci&oacute;n mediante una administraci&oacute;n altamente eficiente de su espacio y una implantaci&oacute;n de hardware. El SCB fue dise&ntilde;ado con una unidad de control distribuida paralela, utilizando una celda de control para cada localidad de almacenamiento. Su capacidad es expandible: puede crecer en ancho y largo, manteniendo constante la complejidad de sus celdas de control. El SCB permite la realizaci&oacute;n simult&aacute;nea de operaciones de escritura y lectura en un solo ciclo de reloj.</font></p>     <p align="justify">&nbsp;</p>  	    <p align="justify"><font face="verdana" size="2"><a href="/pdf/jart/v2n3/v2n3a2.pdf" target="_blank">DESCARGAR ART&Iacute;CULO EN FORMATO PDF</a></font></p> 	    ]]></body>
<body><![CDATA[<p align="justify">&nbsp;</p>  	    <p align="justify"><font face="verdana" size="2"><b>References</b></font></p>  	    <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;1&#93;&nbsp;Hwang K. Advanced Computer Architecture: Parallelism, Scalability, Programmability. McGraw&#45;Hill, 1993.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4815881&pid=S1665-6423200400030000200001&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>  	    <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;2&#93; Thin&#45;fries J. G., Vassiliadis S., Pechanek G. G., Johnson H. D. &amp; Green D. M. To Processing Unit Flexible for Multiprocessor Machine Organizations. Instrumentation and Development, vol. 3, not. 4, pages 20&#45;32, 1994.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4815883&pid=S1665-6423200400030000200002&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p> 	    <!-- ref --><p align="justify"><font face="verdana" size="2"> &#91;3&#93; Jim&eacute;nez&#45;Flores A. &amp; De Luca P. A., Design of a Flexible and Adaptive Router for Parallel Systems. Computation International Congress CIC'99. IPN, M&eacute;xico.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4815885&pid=S1665-6423200400030000200003&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --> </font></p> 	    <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;4&#93; Delgado&#45;Frias J., Vassiliadis S, Johnson H. D., Summerville D. &amp; De Luca A. A Processing Unit for Multiprocesor Organizations. Department of Electrical Engineering, State University of New York at Binghamton. 1996.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4815887&pid=S1665-6423200400030000200004&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --> </font></p> 	    ]]></body>
<body><![CDATA[<!-- ref --><p align="justify"><font face="verdana" size="2">&#91;5&#93; Duato, J. &amp; Sudhakar Y. Interconnection Networks: an engineering approach. IEEE Computer Society Press, 1997.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4815889&pid=S1665-6423200400030000200005&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>  	    <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;6&#93; McHugh J. A. Algorithmic Graph Theory. Prentice&#45;Hall, 1990.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4815891&pid=S1665-6423200400030000200006&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>  	    <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;7&#93; Park J., Vassiliadis S. &amp; Cold Thin J. G. Router Architecture for Oblivious Routing Algorithms. Parallel Computing Technologies (PaCT&#45;93), Obninsk, Russia, 1993.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4815893&pid=S1665-6423200400030000200007&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2"> &#91;8&#93; Culler D. E., Singh J. P., and Gupta A. Parallel Computer Architecture: A hardware/Software Approach. Morgan Kaufmann Publishers Inc., 1999, pp. 1025.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4815895&pid=S1665-6423200400030000200008&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p> 	    <!-- ref --><p align="justify"><font face="verdana" size="2"> &#91;9&#93; Tanenbaum A. S., Structured Computer Organization. Prentice Hall Inc., 1999.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4815897&pid=S1665-6423200400030000200009&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>  	    ]]></body>
<body><![CDATA[<!-- ref --><p align="justify"><font face="verdana" size="2">&#91;10&#93; Jay C. VHDL and Synthesis Tools Provide to Generic Design Entry Platform Into FPGAs, PLDs and ASICs. Microprocessors and Microsystems, Volume 17, Issue 7, September 1993, 391&#45;398.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4815899&pid=S1665-6423200400030000200010&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>  	    <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;11&#93;&nbsp;Dally W. J., Chao L., Chien A. A., Hassoun S., Horwat W., Kaplan J., Song P., Scott B. T. Architecture of to Message&#45;Driven Processor. 25 Years ISCA: Retrospectives and Reprints, pp 337&#45;344, 1998.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4815901&pid=S1665-6423200400030000200011&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>  	    <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;12&#93; Tamir Y. and Frazier G.L. Dynamically Allocated Multi&#45;queue Buffers for VLSI Communication Switches. IEEE Trans. On Computers, volume 41, Not. 6 pp. 725&#45;737, June, 1992.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4815903&pid=S1665-6423200400030000200012&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --> </font></p> 	    <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;13&#93; VHDL Reference Guide. Xilinx Inc., 1999.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4815905&pid=S1665-6423200400030000200013&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --> </font></p> 	    <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;14&#93; Pellerin D., Taylor D. VHDL. Made Easy. Prentice Hall PTR., 1997.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4815907&pid=S1665-6423200400030000200014&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     ]]></body>
<body><![CDATA[ ]]></body><back>
<ref-list>
<ref id="B1">
<label>1</label><nlm-citation citation-type="book">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Hwang]]></surname>
<given-names><![CDATA[K.]]></given-names>
</name>
</person-group>
<source><![CDATA[Advanced Computer Architecture: Parallelism, Scalability, Programmability]]></source>
<year>1993</year>
<publisher-name><![CDATA[McGraw-Hill]]></publisher-name>
</nlm-citation>
</ref>
<ref id="B2">
<label>2</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Thin-fries]]></surname>
<given-names><![CDATA[J. G.]]></given-names>
</name>
<name>
<surname><![CDATA[Vassiliadis]]></surname>
<given-names><![CDATA[S.]]></given-names>
</name>
<name>
<surname><![CDATA[Pechanek]]></surname>
<given-names><![CDATA[G. G.]]></given-names>
</name>
<name>
<surname><![CDATA[Johnson]]></surname>
<given-names><![CDATA[H. D.]]></given-names>
</name>
<name>
<surname><![CDATA[Green]]></surname>
<given-names><![CDATA[D. M.]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[To Processing Unit Flexible for Multiprocessor Machine Organizations]]></article-title>
<source><![CDATA[Instrumentation and Development]]></source>
<year>1994</year>
<volume>3</volume>
<numero>4</numero>
<issue>4</issue>
<page-range>20-32</page-range></nlm-citation>
</ref>
<ref id="B3">
<label>3</label><nlm-citation citation-type="book">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Jiménez-Flores]]></surname>
<given-names><![CDATA[A.]]></given-names>
</name>
<name>
<surname><![CDATA[De Luca]]></surname>
<given-names><![CDATA[P. A.]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Design of a Flexible and Adaptive Router for Parallel Systems]]></article-title>
<source><![CDATA[Computation International Congress CIC'99]]></source>
<year></year>
<publisher-name><![CDATA[IPN]]></publisher-name>
</nlm-citation>
</ref>
<ref id="B4">
<label>4</label><nlm-citation citation-type="book">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Delgado-Frias]]></surname>
<given-names><![CDATA[J.]]></given-names>
</name>
<name>
<surname><![CDATA[Vassiliadis]]></surname>
<given-names><![CDATA[S]]></given-names>
</name>
<name>
<surname><![CDATA[Johnson]]></surname>
<given-names><![CDATA[H. D.]]></given-names>
</name>
<name>
<surname><![CDATA[Summerville]]></surname>
<given-names><![CDATA[D.]]></given-names>
</name>
<name>
<surname><![CDATA[De Luca]]></surname>
<given-names><![CDATA[A.]]></given-names>
</name>
</person-group>
<source><![CDATA[A Processing Unit for Multiprocesor Organizations]]></source>
<year>1996</year>
<publisher-name><![CDATA[Department of Electrical Engineering, State University of New York at Binghamton]]></publisher-name>
</nlm-citation>
</ref>
<ref id="B5">
<label>5</label><nlm-citation citation-type="book">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Duato]]></surname>
<given-names><![CDATA[J.]]></given-names>
</name>
<name>
<surname><![CDATA[Sudhakar]]></surname>
<given-names><![CDATA[Y.]]></given-names>
</name>
</person-group>
<source><![CDATA[Interconnection Networks: an engineering approach]]></source>
<year>1997</year>
<publisher-name><![CDATA[IEEE Computer Society Press]]></publisher-name>
</nlm-citation>
</ref>
<ref id="B6">
<label>6</label><nlm-citation citation-type="book">
<person-group person-group-type="author">
<name>
<surname><![CDATA[McHugh]]></surname>
<given-names><![CDATA[J. A.]]></given-names>
</name>
</person-group>
<source><![CDATA[Algorithmic Graph Theory]]></source>
<year>1990</year>
<publisher-name><![CDATA[Prentice-Hall]]></publisher-name>
</nlm-citation>
</ref>
<ref id="B7">
<label>7</label><nlm-citation citation-type="">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Park]]></surname>
<given-names><![CDATA[J.]]></given-names>
</name>
<name>
<surname><![CDATA[Vassiliadis]]></surname>
<given-names><![CDATA[S.]]></given-names>
</name>
<name>
<surname><![CDATA[Cold Thin]]></surname>
<given-names><![CDATA[J. G.]]></given-names>
</name>
</person-group>
<source><![CDATA[Router Architecture for Oblivious Routing Algorithms]]></source>
<year>1993</year>
<publisher-loc><![CDATA[Obninsk ]]></publisher-loc>
</nlm-citation>
</ref>
<ref id="B8">
<label>8</label><nlm-citation citation-type="book">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Culler]]></surname>
<given-names><![CDATA[D. E.]]></given-names>
</name>
<name>
<surname><![CDATA[Singh]]></surname>
<given-names><![CDATA[J. P.]]></given-names>
</name>
<name>
<surname><![CDATA[Gupta]]></surname>
<given-names><![CDATA[A.]]></given-names>
</name>
</person-group>
<source><![CDATA[Parallel Computer Architecture: A hardware/Software Approach]]></source>
<year>1999</year>
<page-range>1025</page-range><publisher-name><![CDATA[Morgan Kaufmann Publishers Inc.]]></publisher-name>
</nlm-citation>
</ref>
<ref id="B9">
<label>9</label><nlm-citation citation-type="book">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Tanenbaum]]></surname>
<given-names><![CDATA[A. S.]]></given-names>
</name>
</person-group>
<source><![CDATA[Structured Computer Organization]]></source>
<year>1999</year>
<publisher-name><![CDATA[Prentice Hall Inc.]]></publisher-name>
</nlm-citation>
</ref>
<ref id="B10">
<label>10</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Jay]]></surname>
<given-names><![CDATA[C.]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[VHDL and Synthesis Tools Provide to Generic Design Entry Platform Into FPGAs, PLDs and ASICs]]></article-title>
<source><![CDATA[Microprocessors and Microsystems]]></source>
<year>Sept</year>
<month>em</month>
<day>be</day>
<volume>17</volume>
<numero>7</numero>
<issue>7</issue>
<page-range>391-398</page-range></nlm-citation>
</ref>
<ref id="B11">
<label>11</label><nlm-citation citation-type="">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Dally]]></surname>
<given-names><![CDATA[W. J.]]></given-names>
</name>
<name>
<surname><![CDATA[Chao]]></surname>
<given-names><![CDATA[L.]]></given-names>
</name>
<name>
<surname><![CDATA[Chien]]></surname>
<given-names><![CDATA[A. A.]]></given-names>
</name>
<name>
<surname><![CDATA[Hassoun]]></surname>
<given-names><![CDATA[S.]]></given-names>
</name>
<name>
<surname><![CDATA[Horwat]]></surname>
<given-names><![CDATA[W.]]></given-names>
</name>
<name>
<surname><![CDATA[Kaplan]]></surname>
<given-names><![CDATA[J.]]></given-names>
</name>
<name>
<surname><![CDATA[Song]]></surname>
<given-names><![CDATA[P.]]></given-names>
</name>
<name>
<surname><![CDATA[Scott]]></surname>
<given-names><![CDATA[B. T.]]></given-names>
</name>
</person-group>
<source><![CDATA[Architecture of to Message-Driven Processor. 25 Years ISCA: Retrospectives and Reprints]]></source>
<year>1998</year>
<page-range>337-344</page-range></nlm-citation>
</ref>
<ref id="B12">
<label>12</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Tamir]]></surname>
<given-names><![CDATA[Y.]]></given-names>
</name>
<name>
<surname><![CDATA[Frazier]]></surname>
<given-names><![CDATA[G.L.]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Dynamically Allocated Multi-queue Buffers for VLSI Communication Switches]]></article-title>
<source><![CDATA[IEEE Trans. On Computers]]></source>
<year>June</year>
<month>, </month>
<day>19</day>
<volume>41</volume>
<page-range>725-737</page-range></nlm-citation>
</ref>
<ref id="B13">
<label>13</label><nlm-citation citation-type="book">
<source><![CDATA[VHDL Reference Guide]]></source>
<year>1999</year>
<publisher-name><![CDATA[Xilinx Inc.]]></publisher-name>
</nlm-citation>
</ref>
<ref id="B14">
<label>14</label><nlm-citation citation-type="book">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Pellerin]]></surname>
<given-names><![CDATA[D.]]></given-names>
</name>
<name>
<surname><![CDATA[Taylor]]></surname>
<given-names><![CDATA[D.]]></given-names>
</name>
</person-group>
<source><![CDATA[VHDL. Made Easy]]></source>
<year>1997</year>
<publisher-name><![CDATA[Prentice Hall PTR.]]></publisher-name>
</nlm-citation>
</ref>
</ref-list>
</back>
</article>
