A Low–Complexity current–mode WTA circuit based on CMOS Quasi–FG Inverters

Circuito WTA en modo de corriente y baja complejidad, basado en inversores Quasi–FG en CMOS

Jesús Ezequiel Molinar Solís,¹ Luis Abraham Sánchez Gaspariano,² Rodolfo Zolá García Lozano¹, Víctor Ponce Ponce³, Juan J. Ocampo Hidalgo⁴, Herón Molina Lozano³ and Alejandro Díaz Sánchez²

¹ Universidad Autónoma del Estado de México UAEM, Jose Revueltas 17, Tierra Blanca, 55020, Ecatepec, +52 (55) 57873626, MEXICO. Email: jemolinars@uaemex.mx

² National Institute of Astrophysics, Optics and Electronics, INAOE Luis E. Erro 1, Tonantzintla, Puebla, +52 (222) 2663100, MEXICO.

⁴ Universidad Autónoma Metropolitana, UAM, Unidad Azcapotzalco, Av. San Pablo No. 180, Col. Reynosa Tamaulipas, C.P. 02200, México D.F. +52 55 43189000

Article received on February 04, 2009
Accepted on November 09, 2009

Abstract

In this paper, a low–complexity current–mode Winner–Take–All circuit (WTA) of O (n) complexity with logical outputs is presented. The proposed approach employs a Quasi–FG Inverter as the key element for current integration and the computing of the winning cell. The design was implemented in a double–poly, three metal layers, 0.5µm CMOS technology. The circuit exhibits a good accuracy–speed tradeoff when compared to other reported WTA architectures.

Keywords. Winner–take–all, neural networks, analog circuits.

En este artículo, se presenta un circuito "ganador toma todo" (WTA) de baja complejidad en modo de corriente con salidas digitales. La propuesta se basa en el uso de un inversor que utiliza la técnica de Quasi–FG, el cual, realiza una integración de corriente y el cómputo de la celda ganadora. El diseño fue implementado usando una tecnología de doble polisilicio y tres capas de metal para interconexión en tecnología CMOS de 0.5µm. El circuito presenta buena precisión y velocidad en comparación con otras arquitecturas WTA existentes.

Palabras clave: Ganador toma todo, redes neuronales, circuitos analógicos.

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