Performance of a new bus assignment algorithm for an ATM switch fabric

 

J. Sánchez¹, D. Torres², E. Ruiz¹ & M. Guzmán²

 

¹ CICESE, Depto. de Electrónica y Telecomunicaciones, Km. 107 Carretera Tijuana-Ensenada, Ensenada, B.C., 22860, México. Tel:(646)1744502-06, Fax: (646)1750554, e-mail: jasan@cicese.mx

² Centro de Investigación y de Estudios Avanzados del IPN, Unidad Guadalajara, Prol. López Mateos Sur 590, Guadalajara, Jal., México.

 

Received: May 24^th, 2002.
Accepted: February 19^th, 2003.

 

Abstract

This paper presents the results of the performance evaluation, through analytical and simulation models, of a High Speed Packet Switch with a New Bus Assignment Algorithm, designed and developed at the Research and Advanced Studies Center of National Polytechnic Institute in Guadalajara, México (CINVESTAV-GDL). The analytical model is tested under two different arrival processes: Binomial and Poisson distributions. The simulation model is tested with two bus assignment algorithms: Fixed Start and Rotated Start . The performance parameters considered are: Cell Loss Rate, Delay and Throughput.

Keywords: ATM Switch, Bus assignment algorithm, Cell loss rate, Poison arrivals, Throughput.

 

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References

[1] Nail, A., Nihat, S., Oguz, C. & Sohraby K. An Advanced Teletraffic Analysis Package, IEEE Communication Magazine, 36, (8), 84-87 1998.         [ Links ]

[2] Pitts, J.M. & Schormans, J.A., Introduction to ATM Design and Performance: With Application Analysis Software, (John Wiley and Sons, England), 1996.         [ Links ]

[3] Higginbottom, G. N. Performance Evaluation of Communication Networks, (Artech House Publishers, Norwood MA), First Edition, 1998.         [ Links ]

[4] Torres, D., Larios, A. & Guzman, M., Routing Chip Based on a Modified Tree for ATM, IP and Ethernet: Hard/Software Co-design, Proceedings of^: IEEEISCASS 99, (IEEE, Orlando FL), 1, 427-430 1999.         [ Links ]

[5] Torres, D., González, J., Guzman, M. & Nuñez, L. A New Bus Assignment in a Designed Shared Bus Switch Fabric, Proceedings of IEEE SSCASS 99,(IEEE, Orlando FL), 1, 423-426 1999.         [ Links ]

[6] González, J. Architecture, Design and Implementation of a High Speed Cell Switch Fabric, (CINVESTAV Guadalajara), M. Sc. Thesis, 1998.         [ Links ]

[7] Nunez, L., Verification of the elements of a High Speed Cell Switch Fabric, (CINVESTAV Guadalajara), M. Sc. Thesis, 2000.         [ Links ]

[8] Hluchyj, M. G. & Karol M.J., Queueing in High performance Packet Switching,IEEE JSAC 6, (9), 1587-1597 (1988). , Vol. 6, No. 9, 1988, pp: 1587-1597.         [ Links ]

[9] Leonard, K., Queueing Systems Volumen I: Theory, (John Wiley and Sons, New York), First Edition, 1975.         [ Links ]

[10] Cooper, R., Introduction to Queuing Theory, (The Macmillan Company, New York), 1972.         [ Links ]

[11] Papoulis, A. Probability, Random Variables and Stochastic Processes, (Mc Graw Hill, USA), 666 1991.         [ Links ]

[12] MIL3 Inc., OPNET Modeiing Manual, version 5, (MIL3, Inc) http://www.mil3.com 1988.         [ Links ]

[13] Tobagi, F.A., Fast packet Switch architecture for Broadband Integrated Services Digital Networks, Proc. IEE, 78,(1), 133-166, 1990.         [ Links ]