SciELO - Scientific Electronic Library Online

vol.14 issue3EditorialA Multi-Agent Architecture to Support Communities of Practice in Organizations author indexsubject indexsearch form
Home Pagealphabetic serial listing  

Services on Demand




Related links

  • Have no similar articlesSimilars in SciELO


Computación y Sistemas

Print version ISSN 1405-5546

Comp. y Sist. vol.14 n.3 México Jan./Mar. 2011




New High–Performance Full Adders Using an Alternative Logic Structure


Nuevos sumadores de alto desempeño utilizando una estructura lógica alternativa


Mónico Linares Aranda1 and Mariano Aguirre Hernández2


1 Instituto Nacional de Astrofísica, Óptica y Electrónica Apartado postal 51 y 216, C.P. 72000, Puebla, Pue. México. E mail:

2 Intel Corporation, Communications Research Center, México. Email:


Article received on March 24, 2009
Accepted on October 20, 2009



This paper presents two new high–speed low–power 1–bit full–adder cells using an alternative logic structure, and the logic styles DPL and SR–CPL. The adders were designed using electrical parameters of a 0.35µm Complementary Metal–Oxide–Semiconductor (CMOS) process, and were compared with various adders published previously, with regards of power–delay product. To validate the performance simulation results of one of the proposed adders, an 8–bits pipelined multiplier was fabricated using a 0.35µm CMOS technology, and it showed to provide superior performance.

Keywords: Full–adder, Low–power, Multiplier, Pipeline.



En este artículo se presentan dos nuevos sumadores de 1–bit de alta velocidad y bajo consumo de potencia, utilizando en su diseño una estructura lógica alternativa y los estilos lógicos de circuitos DPL y SR–CPL. Los nuevos sumadores fueron comparados con diversos sumadores recientemente publicados en la literatura considerando el producto potencia–retardo, principal figura de mérito de circuitos aritméticos. Con el fin de validar los resultados obtenidos de simulación, uno de los sumadores fue aplicado al diseño y fabricación de un multiplicador en "pipeline" de 8–bits utilizando la tecnología CMOS de 0.35µm. Los resultados experimentales obtenidos mostraron un desempeño superior.

Palabras clave: Sumador completo, Baja potencia, Multiplicador, Pipeline.





This work was partially supported by Conacyt–Mexico under grant #51511–Y and scholarship #112784.



1. Abu–Shama E., Elchouemi A., Sayed S. & Bayoumi M. (1995). An efficient low power basic cell for adders, IEEE International Symposium on Circuits and Systems, Rio de Janeiro, Brazil, 306–308.         [ Links ]

2. Agarwal S., Pavankumar V. K., & Yokesh R. (2008). Energy–efficient, high performance circuits for arithmetic units, 21st International Conference on VLSI Design, Hyderabad, India, 371–376.         [ Links ]

3. Aguirre–Hernández, M. & Linares–Aranda, M. (2004). Low–power low–voltage 1–bit CMOS full adder for energy–efficient multimedia applications. ICED/CASTOUR, Veracruz, México. Retrieved from: http://www–        [ Links ]

4. Aguirre H. M. (2006). Diseño de un codificador fractal de imágenes con uso eficiente de energía, Tesis de Doctorado, Instituto Nacional de Astrofísica, Óptica y Electrónica, Puebla, Pué., México.         [ Links ]

5. Aguirre M. & Linares M. (2005), An alternative logic approach to implement high–speed low–power full adder cells, 18th Symposium on Integrated Circuits and Systems Design SBCCI'05, Florianopolis, Brazil, 166–171.         [ Links ]

6. Alhalabi B. & Al–Sheraidah A. (2001), A novel low–power multiplexer–based full adder cell, 8th IEEE International Conference on Electronics, Circuits and Systems, Malta, 1433–1436        [ Links ]

7. Chang C. H., Zhang M., & Gu J. (2003). A novel low power low voltage full adder cell. 3rd International Symposium on Image and Signal Processing and Analysis, Rome, Italy, 454–458.         [ Links ]

8. Chu K. M. & Pulfrey D. L. (1987). A comparison of CMOS circuit techniques: differential cascode voltage switch logic versus conventional logic, IEEE Journal of Solid–State Circuits, 22(4), 528–532.         [ Links ]

9. Fayed A. & Bayoumi M. (2001). A Low–Power 10–transistor full adder cell for embedded architectures, IEEE International Symposium on Circuits and Systems ISCAS 2001, Sydney, NSW , Australia, 226–229.         [ Links ]

10. Goel S., Kumar A., & Bayoumi M. A. (2006). Design of robust, energy–efficient full adders for deep–submicrometer design using hybrid–CMOS logic style, IEEE Transactions on Very Large Scale Integration Systems, 14(12),1309–1321.         [ Links ]

11. Him C., Kim H. & Ha S. (2001). Dynamic voltage scheduling technique for low–power multimedia applications using buffers, International Symposium on Low Power Electronics and Design. ISLPED'01, Huntington Beach, CA , USA, 34–39.         [ Links ]

12. Hodges, D. A., Jackson H. G. & Saleh, R. A. (2003). Analysis and Design of Digital Integrated Circuits in Deep Submicron Technology, (Third edition), Boston: McGraw–Hill Higher Education. HSPICE User Guide: Simulation and analysis, Version B–2008.09. Synopsys September 2008. Retrieved_from:        [ Links ]

13. Mahmoud H. A. & Bayoumi M. A. (1999). A 10–transistor low–power high–speed full adder cell, IEEE International Symposium on Circuits and Systems ISCAS 1999, Orlando, FL, USA, 43–46.         [ Links ]

14. Moalemi V. & Afzali–Kusha A. (2007). Subthreshold 1–bit full adder cells in sub–100 nm technologies, IEEE Computer Society Annual Symposium on VLSI, Porto Alegre, Brasil, 514–515. Nanosim User Guide, Version V–2004.06, June 2004. Synopsys, June 2004 Retrieved from:        [ Links ]

15. Nishitani T. (1999). VLSI for digital signal processing low–power architectures for programmable multimedia processors, IEICE transactions on fundamentals of electronics, communications and computer sciences, E82–A(2),184–196.         [ Links ]

16. Pacheco B. D. & Linares A. M. (2004). A low power and high speed CMOS voltage–controlled ring oscillator, IEEE International Symposium on Circuits and Systems ISCAS 2004, Vancouver, Canada, (4) 752–755.         [ Links ]

17. Radhakrishnan D. (2001). Low–voltage low–power CMOS full adder, IEE Proceedings on Circuits Devices and Systems, 148(1), 19–24.         [ Links ]

18. Shams A. M. & Bayoumi M. A. (1998). A structured approach for designing low Power adders, Conference Record of the Thirty–First Asilomar Conference on Signals, Systems and Computers. Pacific Grove, CA , USA, 1, 757–761.         [ Links ]

19. Shams, A. M. & Bayoumi M. A. (1998). A novel low–power building block CMOS cell for adders, IEEE International Symposium on Circuits and Systems ISCAS`98, Monterey, CA , USA, 2, 153– 156.         [ Links ]

20. Shams A. M., Darwish T. K. & Bayoumi M. A. (2002). Performance analysis of low–power 1–bit CMOS full adder cell, IEEE Transactions on Very Large Scale Integration Systems (VLSI), 10(1), 20–29.         [ Links ]

21. Singh M., Giacomotto C., Zeydel B. & Oklobdzija V. (2007). Logic style comparison for ultra low–power operation in 65nm technology, International Workshop on Power and Timing Modeling, Optimization and Simulation, Gothenburg, Sweden, 181–190.         [ Links ]

22. Suzuki M., Ohkubo N., Yamanaka T., Shimizu A. & Sasaki K. (1993). A 1.5ns 32–b CMOS ALU in double pass–transistor logic, IEEE Journal of Solid–State Circuits, 28(11), 1145–1151.         [ Links ]

23. Weste, N. & Eshraghian, K. (1993). Principles of CMOS VLSI design: a system perspective, Second edition. Addison–Wesley.         [ Links ]

24. Wey I., Huang C. & Chow H. (2002). A new low–voltage CMOS 1–bit full adder for high performance applications, IEEE Asia–Pacific Conference on ASIC 2002, Taipei, Taiwan. 21–24.         [ Links ]

25. Wu A. & Ng C. K. (1997). High performance low power low voltage adder, Electronic Letters, 33(8), 681–682.         [ Links ]

26. Yano K., Yamanaka, T., Nishida, T., Saito, M., Shimohigashi, K., & Shimizu, A. (1990). A 3.8ns CMOS 16 × 16–b multiplier using complementary pass–transistor logic", IEEE Journal of Solid–State Circuits, 25(2), 388–395.         [ Links ]

27. Zhuang N. & Wu H. (1992). A new design of the CMOS full adder, IEEE Journal of Solid–State Circuits, 27(5), 840–844.         [ Links ]

28. Zimmerman R. & Fichtner W. (1997). Low–power logic styles: CMOS versus pass–transistor logic, IEEE Journal of Solid–State Circuits, 32(7), 1079–1090.         [ Links ]

Creative Commons License All the contents of this journal, except where otherwise noted, is licensed under a Creative Commons Attribution License