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Computación y Sistemas

Print version ISSN 1405-5546

Comp. y Sist. vol.10 n.3 México Jan./Mar. 2007

 

Artículos

 

Automatic Synthesis of Electronic Circuits using Genetic Algorithms

 

Síntesis Automática de Circuitos Electrónicos usando Algoritmos Genéticos

 

Esteban Tlelo Cuautle1, Miguel Aurelio Duarte Villaseñor2, Carlos Alberto Reyes García3 and Gerardo Reyes Salgado4

 

1 INAOE, Department of Electronics
e.tlelo@ieee.org

2 INAOE, Department of Electronics
miauduvi@inaoep.mx

3 INAOE, Department of Computer Sciences

4 CENIDET, Department of Computer Sciences

 

Article received on February 01, 2007; accepted on June 23, 2007

 

Abstract

An automatic synthesis method based on the application of genetic algorithms (GAs) is described for the synthesis of voltage followers (VFs), which are designed using CMOS integrated circuit technology of 0.35µm. It is shown the usefulness of the nullor element to model the ideal behavior of the VF, and to codify its topology using a chromosome which is divided into four genes: gene of small–signal (genSS), gene of synthesis of the MOSFET (genSMos), gene of bias (genBias), and gene of synthesis of current mirrors (genCM); this last one to synthesize ideal current sources used in the biasing of the circuits with CMOS current mirrors.

The proposed synthesis method has been programmed in MatLab, and it uses T–SPICE to evaluate the fitness of the VFs at the transistor level of abstraction. In this manner, the method selects the more appropriated VFs by elitism. Finally, it is shown the behavior of the GA to synthesize practical VFs. As a result, it is shown the synthesis of eight CMOS compatible VFs, and their applications are briefly discussed.

Keywords: Evolutionary electronics, circuit synthesis, voltage follower, nullor.

 

Resumen

Se describe un método de síntesis automática basado en la aplicación de algoritmos genéticos (GAs) para la síntesis de seguidores de voltaje (VFs), los cuales son diseñados usando tecnología CMOS de circuitos integrados de 0.35µm. Se demuestra la utilidad del elemento anulador para modelar el comportamiento ideal del VF, y para codificar su topología usando un cromosoma que es dividido en cuatro genes: gen de pequeña señal (genSS), gen de síntesis del MOSFET (genSMos), gen de polarización (genBias), y gen de síntesis de espejos de corriente (genCM); este último para sintetizar las fuentes de corriente ideales utilizadas en la polarización de los circuitos por espejos de corriente CMOS.

El método de síntesis propuesto se ha programado en MatLab, y usa T–SPICE para evaluar la aptitud de los VFs en el nivel de abstracción de transistor. De esta manera, el método selecciona los VFs más apropiados por elitismo. Finalmente, se muestra el comportamiento del GA para sintetizar VFs prácticos. Como resultado, se muestra la síntesis de ocho VFs compatibles con CMOS, y sus aplicaciones se discuten brevemente.

Palabras clave: Electrónica evolutiva, síntesis de circuitos, seguidor de voltaje, anulador.

 

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Acknowledgment

This work is supported by CONACyT/MEXICO with the project number 48396–Y.

 

References

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2. Koza, J.R., Jones, L.W., Keane, M.A., Streeter, M.J., Al–Sakran, A.H., Toward automated design of industrial–strength analog circuits by means of genetic programming, In Genetic Programming Theory and Practice II. (Kluwer Academic Publishers Chapter 8:121–142, 2004).        [ Links ]

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4. Salem Z. R., M. A. Pacheco, M. Vellasco, Evolutionary Electronics: Automatic design of electronic circuits and systems by genetic algorithms, (CRC Press, 2002).        [ Links ]

5. Tlelo–Cuautle, E., Torres–Muñoz, D., Torres–Papaqui, L., "On the computational synthesis of CMOS voltage followers" IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E88–A(12): 3479–3484 (2005).        [ Links ]

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10. Tlelo–Cuautle, E., Duarte–Villaseñor M.A., Reyes–García, C.A., Sánchez–López, C., Reyes–Salgado, G., Fakhfakh, M., Loulou, M., Designing VFs by applying genetic algorithms from nullator–based descriptions, 18th European Conference on Circuit Theory and Design, Sevilla, Spain, August 26–30, 2007.        [ Links ]

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