Computación y Sistemas
Print version ISSN 1405-5546
This paper presents two new high-speed low-power 1-bit full-adder cells using an alternative logic structure, and the logic styles DPL and SR-CPL. The adders were designed using electrical parameters of a 0.35µm Complementary Metal-Oxide-Semiconductor (CMOS) process, and were compared with various adders published previously, with regards of power-delay product. To validate the performance simulation results of one of the proposed adders, an 8-bits pipelined multiplier was fabricated using a 0.35µm CMOS technology, and it showed to provide superior performance.
Keywords : Full-adder; Low-power; Multiplier; Pipeline.