Resumen

SANDOVAL-IBARRA, F.; SANTANA, J.; MORAN-SERNA, J. A.  y  SUAREZ-LIZARRAGA, G.. A simple procedure to design Glitch-less switched-current cells. Rev. mex. fis. [online]. 2002, vol.48, n.3, pp.182-185. ISSN 0035-001X.

The description of non-idealities in Cascode Switched-Current (SI) cell as well as its application in analog signal processing is described. A test chip (CMOS, 1.5 μm, N-well, 0-5 V) was designed to verify that the proposed method works successfully in the magnitude glitch reduction problem.

Palabras llave : Integrated circuits.

        · resumen en Español     · texto en Inglés     · Inglés ( pdf )