E. García, M. Guzmán & D. Torres
Centro de Investigación y Estudios Avanzados del IPN, Unidad Guadalajara Prol. López Mateos Sur # 590 Guadalajara, Jalisco, México. dtorres@gdl.cinvestav.mx
Received: October 14th, 2002.
Accepted: May 30th, 2005.
]]> Abstract
This paper presents a VLSI (Very Large Scale Integration) implementation of high punctured convolutional codes. We present a new circuit architecture that is capable of processing up to 10 convolutional codes rate (n-1)/n with the constraint length-7 derived by the puncturing technique from the basic rate-1/2. The present circuit was designed in order to complete an existing Viterbi decoder core, adding some extra functionality such as a convolutional encoder, differential encoder/decoder, punctured convolutional encoder and symbol insertion to depuncture the received data. This extra functionality includes 10 different programmable coding rates without the need to add additional logic in the system implementation, while other existing coders need it to attain higher coding rates. Therefore, a single chip solution is presented. The design was implemented in VHDL (Very High Speed Integrated Circuit Hardware Description Language) synthesized in Synopsystool, and tested in a FPGA. Functional verification was done, by means of simulation, to ensure that the circuit implements intended functionality. Such simulations were executed using Synopsys and a Sun Ultra Sparc 10 workstation. Different bit error probability performance curves show an agreement between simulated and theoretical values.
Keywords: Convolutional Coding, Viterbi Decoding, Punctured Codes.
Resumen
El presente trabajo presenta el diseño, la implementación y la verificación de un circuito con código convolucional perforado para completar un decodificador de Viterbi. A esta versión se le añadieron las siguientes funcionalidades: codificador convolucional, codificador/decodificador diferencial, codificador convolucional perforado con inserción de símbolos. Además, se incluyeron 10 diferentes razones de codificación, superando versiones existentes en el mercado. El circuito desarrollado no requiere lógica externa para realizar el perforado, por lo que puede implementarse en un solo chip. El diseño fue implementado en VHDL, sintetizado usando la herramienta Synopsys, y probado en un FPGA. Se empleó una estación de trabajo Ultra Sparc 10. La verificación funcional permitió probar que el diseño satisface los requerimientos formulados. Finalmente, se presentan diferentes curvas que demuestran una buena coincidencia de los valores obtenidos de la probabilidad de error con los teóricos.
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