<?xml version="1.0" encoding="ISO-8859-1"?><article xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<front>
<journal-meta>
<journal-id>1665-6423</journal-id>
<journal-title><![CDATA[Journal of applied research and technology]]></journal-title>
<abbrev-journal-title><![CDATA[J. appl. res. technol]]></abbrev-journal-title>
<issn>1665-6423</issn>
<publisher>
<publisher-name><![CDATA[Universidad Nacional Autónoma de México, Instituto de Ciencias Aplicadas y Tecnología]]></publisher-name>
</publisher>
</journal-meta>
<article-meta>
<article-id>S1665-64232016000100067</article-id>
<article-id pub-id-type="doi">10.1016/j.jart.2015.11.001</article-id>
<title-group>
<article-title xml:lang="en"><![CDATA[Design partitioning and layer assignment for 3D integrated circuits using tabu search and simulated annealing]]></article-title>
</title-group>
<contrib-group>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Sait]]></surname>
<given-names><![CDATA[Sadiq M.]]></given-names>
</name>
<xref ref-type="aff" rid="Aff"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Oughali]]></surname>
<given-names><![CDATA[Feras Chikh]]></given-names>
</name>
<xref ref-type="aff" rid="Aff"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Al-Asli]]></surname>
<given-names><![CDATA[Mohammed]]></given-names>
</name>
<xref ref-type="aff" rid="Aff"/>
</contrib>
</contrib-group>
<aff id="Af1">
<institution><![CDATA[,King Fahd University of Petroleum & Minerals Computer Engineering Department Center for Communications & IT Research]]></institution>
<addr-line><![CDATA[Dhahran ]]></addr-line>
<country>Saudi Arabia</country>
</aff>
<pub-date pub-type="pub">
<day>00</day>
<month>00</month>
<year>2016</year>
</pub-date>
<pub-date pub-type="epub">
<day>00</day>
<month>00</month>
<year>2016</year>
</pub-date>
<volume>14</volume>
<numero>1</numero>
<fpage>67</fpage>
<lpage>76</lpage>
<copyright-statement/>
<copyright-year/>
<self-uri xlink:href="http://www.scielo.org.mx/scielo.php?script=sci_arttext&amp;pid=S1665-64232016000100067&amp;lng=en&amp;nrm=iso"></self-uri><self-uri xlink:href="http://www.scielo.org.mx/scielo.php?script=sci_abstract&amp;pid=S1665-64232016000100067&amp;lng=en&amp;nrm=iso"></self-uri><self-uri xlink:href="http://www.scielo.org.mx/scielo.php?script=sci_pdf&amp;pid=S1665-64232016000100067&amp;lng=en&amp;nrm=iso"></self-uri><abstract abstract-type="short" xml:lang="en"><p><![CDATA[3D integrated circuits (3D-ICs) is an emerging technology with lots of potential. 3D-ICs enjoy small footprint area and vertical interconnections between different dies which allow shorter wirelength among gates. Hence, they exhibit both lesser interconnect delays and power consumption. The design flow of 3D integrated circuits consists of many steps, the first of which is the 3D Partitioning and Layer Assignment. This step has a significant importance as its outcome will influence the performance of subsequent steps. Like other partitioning problems this one is also an NP-hard. The approach taken to address this critical task is the application of iterative heuristics (Sait &amp; Youssef, 1999), as they have been proven to be of great value when it comes to handling such problems. Many aspects have been taken into consideration when attempting to solve this problem. These factors include layer assignment, location of I/O terminals, TSV minimization, and area balancing. Tabu Search and Simulated Annealing are employed and engineered to tackle this task. Results on well-known benchmarks show that both these techniques produce high quality solutions. The average percentage of the area deviation between layers is around 2.4% and the total number of required TSVs is reduced.]]></p></abstract>
<kwd-group>
<kwd lng="en"><![CDATA[Through-silicon via (TSV)]]></kwd>
<kwd lng="en"><![CDATA[3D integrated circuits (3D ICs)]]></kwd>
<kwd lng="en"><![CDATA[Iterative heuristics]]></kwd>
<kwd lng="en"><![CDATA[Tabu search]]></kwd>
<kwd lng="en"><![CDATA[Simulated annealing]]></kwd>
<kwd lng="en"><![CDATA[Combinatorial optimization]]></kwd>
<kwd lng="en"><![CDATA[Multi-way partitioning]]></kwd>
<kwd lng="en"><![CDATA[NP-hard problems]]></kwd>
</kwd-group>
</article-meta>
</front><back>
<ref-list>
<ref id="B1">
<nlm-citation citation-type="journal">
<article-title xml:lang=""><![CDATA[Three-dimensional place and route for FPGAs]]></article-title>
<person-group person-group-type="author">
<name>
<surname><![CDATA[Ababei]]></surname>
<given-names><![CDATA[C.]]></given-names>
</name>
<name>
<surname><![CDATA[Mogal]]></surname>
<given-names><![CDATA[H.]]></given-names>
</name>
<name>
<surname><![CDATA[Bazargan]]></surname>
<given-names><![CDATA[K.]]></given-names>
</name>
</person-group>
<source><![CDATA[IEEE Transactions on Computer-Aided Design of Integrated Circuits &amp; Systems]]></source>
<year>2006</year>
<volume>25</volume>
<numero>6</numero>
<issue>6</issue>
<page-range>1132-40</page-range></nlm-citation>
</ref>
<ref id="B2">
<nlm-citation citation-type="journal">
<article-title xml:lang=""><![CDATA[Chips go vertical [3D IC interconnection]]]></article-title>
<person-group person-group-type="author">
<name>
<surname><![CDATA[Baliga]]></surname>
<given-names><![CDATA[J.]]></given-names>
</name>
</person-group>
<source><![CDATA[Spectrum, IEEE]]></source>
<year>2004</year>
<volume>41</volume>
<numero>3</numero>
<issue>3</issue>
<page-range>43-7</page-range></nlm-citation>
</ref>
<ref id="B3">
<nlm-citation citation-type="">
<article-title xml:lang=""><![CDATA[Through-silicon via and die stacking technologies for microsystems-integration]]></article-title>
<person-group person-group-type="author">
<name>
<surname><![CDATA[Beyne]]></surname>
<given-names><![CDATA[E.]]></given-names>
</name>
<name>
<surname><![CDATA[De Moor]]></surname>
<given-names><![CDATA[P.]]></given-names>
</name>
<name>
<surname><![CDATA[Ruythooren]]></surname>
<given-names><![CDATA[W.]]></given-names>
</name>
<name>
<surname><![CDATA[Labie]]></surname>
<given-names><![CDATA[R.]]></given-names>
</name>
<name>
<surname><![CDATA[Jourdain]]></surname>
<given-names><![CDATA[A.]]></given-names>
</name>
<name>
<surname><![CDATA[Tilmans]]></surname>
<given-names><![CDATA[H.]]></given-names>
</name>
</person-group>
<source><![CDATA[2008 IEEE International Electron Devices Meeting]]></source>
<year>2008</year>
<page-range>1-4</page-range></nlm-citation>
</ref>
<ref id="B4">
<nlm-citation citation-type="">
<article-title xml:lang=""><![CDATA[The road to 3D EDA tool readiness]]></article-title>
<person-group person-group-type="author">
<name>
<surname><![CDATA[Chiang]]></surname>
<given-names><![CDATA[C.]]></given-names>
</name>
<name>
<surname><![CDATA[Sinha]]></surname>
<given-names><![CDATA[S.]]></given-names>
</name>
</person-group>
<source><![CDATA[Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC]]></source>
<year>2009</year>
<page-range>429-36</page-range></nlm-citation>
</ref>
<ref id="B5">
<nlm-citation citation-type="journal">
<article-title xml:lang=""><![CDATA[Demystifying 3D ICs: The pros and cons of going vertical]]></article-title>
<person-group person-group-type="author">
<name>
<surname><![CDATA[Davis]]></surname>
<given-names><![CDATA[W.R.]]></given-names>
</name>
<name>
<surname><![CDATA[Wilson]]></surname>
<given-names><![CDATA[J.]]></given-names>
</name>
<name>
<surname><![CDATA[Mick]]></surname>
<given-names><![CDATA[S.]]></given-names>
</name>
<name>
<surname><![CDATA[Xu]]></surname>
<given-names><![CDATA[J.]]></given-names>
</name>
<name>
<surname><![CDATA[Hua]]></surname>
<given-names><![CDATA[H.]]></given-names>
</name>
<name>
<surname><![CDATA[Mineo]]></surname>
<given-names><![CDATA[C.]]></given-names>
</name>
</person-group>
<source><![CDATA[IEEE Design and Test of Computers]]></source>
<year>2005</year>
<volume>22</volume>
<numero>6</numero>
<issue>6</issue>
<page-range>498-510</page-range></nlm-citation>
</ref>
<ref id="B6">
<nlm-citation citation-type="journal">
<article-title xml:lang=""><![CDATA[Characterization of the ordered weighted averaging operators]]></article-title>
<person-group person-group-type="author">
<name>
<surname><![CDATA[Fodor]]></surname>
<given-names><![CDATA[J.]]></given-names>
</name>
<name>
<surname><![CDATA[Marichal]]></surname>
<given-names><![CDATA[J.-L.]]></given-names>
</name>
<name>
<surname><![CDATA[Roubens]]></surname>
<given-names><![CDATA[M.]]></given-names>
</name>
</person-group>
<source><![CDATA[IEEE Transactions on Fuzzy Systems]]></source>
<year>1995</year>
<volume>3</volume>
<numero>2</numero>
<issue>2</issue>
<page-range>236-40</page-range></nlm-citation>
</ref>
<ref id="B7">
<nlm-citation citation-type="journal">
<article-title xml:lang=""><![CDATA[Fuzzy preference modelling and multicriteria decision support]]></article-title>
<person-group person-group-type="author">
<name>
<surname><![CDATA[Fodor]]></surname>
<given-names><![CDATA[J.]]></given-names>
</name>
<name>
<surname><![CDATA[Roubens]]></surname>
<given-names><![CDATA[M.]]></given-names>
</name>
</person-group>
<source><![CDATA[Theory and Decision Library Series D: System Theory, Knowledge Engineering, and Problem Solving]]></source>
<year>1994</year>
</nlm-citation>
</ref>
<ref id="B8">
<nlm-citation citation-type="book">
<article-title xml:lang=""><![CDATA[Physical design implementation for 3D IC: methodology and tools]]></article-title>
<person-group person-group-type="author">
<name>
<surname><![CDATA[Gerousis]]></surname>
<given-names><![CDATA[V.]]></given-names>
</name>
</person-group>
<source><![CDATA[Proceedings of the 19th International Symposium on Physical Design]]></source>
<year>2010</year>
<page-range>57</page-range><publisher-loc><![CDATA[New York, USA ]]></publisher-loc>
<publisher-name><![CDATA[ACM]]></publisher-name>
</nlm-citation>
</ref>
<ref id="B9">
<nlm-citation citation-type="journal">
<article-title xml:lang=""><![CDATA[New spectral methods for ratio cut partitioning and clustering]]></article-title>
<person-group person-group-type="author">
<name>
<surname><![CDATA[Hagen]]></surname>
<given-names><![CDATA[L.]]></given-names>
</name>
<name>
<surname><![CDATA[Kahng]]></surname>
<given-names><![CDATA[A.B.]]></given-names>
</name>
</person-group>
<source><![CDATA[IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems]]></source>
<year>1992</year>
<volume>11</volume>
<numero>9</numero>
<issue>9</issue>
<page-range>1074-85</page-range></nlm-citation>
</ref>
<ref id="B10">
<nlm-citation citation-type="">
<article-title xml:lang=""><![CDATA[Layer-aware design partitioning for vertical interconnect minimization]]></article-title>
<person-group person-group-type="author">
<name>
<surname><![CDATA[Huang]]></surname>
<given-names><![CDATA[Y.-S.]]></given-names>
</name>
<name>
<surname><![CDATA[Liu]]></surname>
<given-names><![CDATA[Y.-H.]]></given-names>
</name>
<name>
<surname><![CDATA[Huang]]></surname>
<given-names><![CDATA[J.-D.]]></given-names>
</name>
</person-group>
<source><![CDATA[2011 IEEE Computer Society Annual Symposium on VLSI]]></source>
<year>2011</year>
<page-range>144-9</page-range></nlm-citation>
</ref>
<ref id="B11">
<nlm-citation citation-type="book">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Croucher]]></surname>
<given-names><![CDATA[J.]]></given-names>
</name>
</person-group>
<source><![CDATA[Statistics: Making business decisions]]></source>
<year>2002</year>
<publisher-loc><![CDATA[Sydney ]]></publisher-loc>
<publisher-name><![CDATA[McGraw-Hill]]></publisher-name>
</nlm-citation>
</ref>
<ref id="B12">
<nlm-citation citation-type="">
<article-title xml:lang=""><![CDATA[Aggregation and scoring procedures in multicriteria decision making methods]]></article-title>
<person-group person-group-type="author">
<name>
<surname><![CDATA[Fodor]]></surname>
<given-names><![CDATA[J.]]></given-names>
</name>
<name>
<surname><![CDATA[Roubens]]></surname>
<given-names><![CDATA[M.]]></given-names>
</name>
</person-group>
<source><![CDATA[IEEE International Conference on Fuzzy Systems]]></source>
<year>1992</year>
<page-range>1261-7</page-range></nlm-citation>
</ref>
<ref id="B13">
<nlm-citation citation-type="journal">
<article-title xml:lang=""><![CDATA[An upper bound on the value of the standard deviation]]></article-title>
<person-group person-group-type="author">
<name>
<surname><![CDATA[Croucher]]></surname>
<given-names><![CDATA[J.S.]]></given-names>
</name>
</person-group>
<source><![CDATA[Teaching Statistics]]></source>
<year>2004</year>
<volume>26</volume>
<numero>2</numero>
<issue>2</issue>
<page-range>54-5</page-range></nlm-citation>
</ref>
<ref id="B14">
<nlm-citation citation-type="journal">
<article-title xml:lang=""><![CDATA[Multilevel hypergraph partitioning: applications in VLSI domain]]></article-title>
<person-group person-group-type="author">
<name>
<surname><![CDATA[Karypis]]></surname>
<given-names><![CDATA[G.]]></given-names>
</name>
<name>
<surname><![CDATA[Aggarwal]]></surname>
<given-names><![CDATA[R.]]></given-names>
</name>
<name>
<surname><![CDATA[Kumar]]></surname>
<given-names><![CDATA[V.]]></given-names>
</name>
<name>
<surname><![CDATA[Shekhar]]></surname>
<given-names><![CDATA[S.]]></given-names>
</name>
</person-group>
<source><![CDATA[IEEE Transactions on Very Large Scale Integration (VLSI) Systems]]></source>
<year>1999</year>
<volume>7</volume>
<numero>1</numero>
<issue>1</issue>
<page-range>69-79</page-range></nlm-citation>
</ref>
<ref id="B15">
<nlm-citation citation-type="journal">
<article-title xml:lang=""><![CDATA[Study of through-silicon-via impact on the 3-D stacked IC layout]]></article-title>
<person-group person-group-type="author">
<name>
<surname><![CDATA[Kim]]></surname>
<given-names><![CDATA[D.H.]]></given-names>
</name>
<name>
<surname><![CDATA[Athikulwongse]]></surname>
<given-names><![CDATA[K.]]></given-names>
</name>
<name>
<surname><![CDATA[Lim]]></surname>
<given-names><![CDATA[S.K.]]></given-names>
</name>
</person-group>
<source><![CDATA[IEEE Transactions on Very Large Scale Integration (VLSI) Systems]]></source>
<year>2013</year>
<volume>21</volume>
<numero>5</numero>
<issue>5</issue>
<page-range>862-74</page-range></nlm-citation>
</ref>
<ref id="B16">
<nlm-citation citation-type="">
<article-title xml:lang=""><![CDATA[TSV-aware interconnect length and power prediction for 3D stacked ICs]]></article-title>
<person-group person-group-type="author">
<name>
<surname><![CDATA[Kim]]></surname>
<given-names><![CDATA[D.H.]]></given-names>
</name>
<name>
<surname><![CDATA[Mukhopadhyay]]></surname>
<given-names><![CDATA[S.]]></given-names>
</name>
<name>
<surname><![CDATA[Lim]]></surname>
<given-names><![CDATA[S.K.]]></given-names>
</name>
</person-group>
<source><![CDATA[2009 IEEE International Interconnect Technology Conference]]></source>
<year>2009</year>
<page-range>26-8</page-range></nlm-citation>
</ref>
<ref id="B17">
<nlm-citation citation-type="journal">
<article-title xml:lang=""><![CDATA[Statistics for business and economics]]></article-title>
<person-group person-group-type="author">
<name>
<surname><![CDATA[Lee]]></surname>
<given-names><![CDATA[C.-F.]]></given-names>
</name>
<name>
<surname><![CDATA[Lee]]></surname>
<given-names><![CDATA[J.C.]]></given-names>
</name>
<name>
<surname><![CDATA[Lee]]></surname>
<given-names><![CDATA[A.C.]]></given-names>
</name>
</person-group>
<source><![CDATA[The American Statistician]]></source>
<year>2006</year>
<volume>60</volume>
</nlm-citation>
</ref>
<ref id="B18">
<nlm-citation citation-type="journal">
<article-title xml:lang=""><![CDATA[Generic integer linear programming formulation for 3D IC partitioning]]></article-title>
<person-group person-group-type="author">
<name>
<surname><![CDATA[Lee]]></surname>
<given-names><![CDATA[W.Y.]]></given-names>
</name>
<name>
<surname><![CDATA[Jiang]]></surname>
<given-names><![CDATA[I.H.R.]]></given-names>
</name>
<name>
<surname><![CDATA[Mei]]></surname>
<given-names><![CDATA[T.W.]]></given-names>
</name>
</person-group>
<source><![CDATA[Journal of Information Science and Engineering]]></source>
<year>2012</year>
<volume>28</volume>
<numero>6</numero>
<issue>6</issue>
<page-range>1129-44</page-range></nlm-citation>
</ref>
<ref id="B19">
<nlm-citation citation-type="journal">
<article-title xml:lang=""><![CDATA[Fast fixed-outline 3-D IC floorplanning with TSV co-placement]]></article-title>
<person-group person-group-type="author">
<name>
<surname><![CDATA[Li]]></surname>
<given-names><![CDATA[C.-R.]]></given-names>
</name>
<name>
<surname><![CDATA[Mak]]></surname>
<given-names><![CDATA[W.-K.]]></given-names>
</name>
<name>
<surname><![CDATA[Wang]]></surname>
<given-names><![CDATA[T.-C.]]></given-names>
</name>
</person-group>
<source><![CDATA[IEEE Transactions on Very Large Scale Integration (VLSI) Systems]]></source>
<year>2012</year>
<volume>21</volume>
</nlm-citation>
</ref>
<ref id="B20">
<nlm-citation citation-type="journal">
<article-title xml:lang=""><![CDATA[Hierarchical 3-D floorplanning algorithm for wirelength optimization]]></article-title>
<person-group person-group-type="author">
<name>
<surname><![CDATA[Li]]></surname>
<given-names><![CDATA[Z.]]></given-names>
</name>
<name>
<surname><![CDATA[Hong]]></surname>
<given-names><![CDATA[X.]]></given-names>
</name>
<name>
<surname><![CDATA[Zhou]]></surname>
<given-names><![CDATA[Q.]]></given-names>
</name>
<name>
<surname><![CDATA[Cai]]></surname>
<given-names><![CDATA[Y.]]></given-names>
</name>
<name>
<surname><![CDATA[Bian]]></surname>
<given-names><![CDATA[J.]]></given-names>
</name>
<name>
<surname><![CDATA[Yang]]></surname>
<given-names><![CDATA[H.H.]]></given-names>
</name>
</person-group>
<source><![CDATA[IEEE Transactions on Circuits and Systems I: Regular Papers]]></source>
<year>2006</year>
<volume>53</volume>
<numero>12</numero>
<issue>12</issue>
<page-range>2637-46</page-range></nlm-citation>
</ref>
<ref id="B21">
<nlm-citation citation-type="">
<source><![CDATA[MCNC/G benchmarks, MCNC/GSRC benchmarks]]></source>
<year></year>
</nlm-citation>
</ref>
<ref id="B22">
<nlm-citation citation-type="journal">
<article-title xml:lang=""><![CDATA[Equation of state calculations by fast computing machines]]></article-title>
<person-group person-group-type="author">
<name>
<surname><![CDATA[Metropolis]]></surname>
<given-names><![CDATA[N.]]></given-names>
</name>
<name>
<surname><![CDATA[Rosenbluth]]></surname>
<given-names><![CDATA[A.W.]]></given-names>
</name>
<name>
<surname><![CDATA[Rosenbluth]]></surname>
<given-names><![CDATA[M.N.]]></given-names>
</name>
<name>
<surname><![CDATA[Teller]]></surname>
<given-names><![CDATA[A.H.]]></given-names>
</name>
<name>
<surname><![CDATA[Teller]]></surname>
<given-names><![CDATA[E.]]></given-names>
</name>
</person-group>
<source><![CDATA[The Journal of Chemical Physics]]></source>
<year>1953</year>
<volume>21</volume>
<numero>6</numero>
<issue>6</issue>
<page-range>1087-92</page-range></nlm-citation>
</ref>
<ref id="B23">
<nlm-citation citation-type="journal">
<article-title xml:lang=""><![CDATA[Interconnect-based design methodologies for three-dimensional integrated circuits]]></article-title>
<person-group person-group-type="author">
<name>
<surname><![CDATA[Pavlidis]]></surname>
<given-names><![CDATA[V.F.]]></given-names>
</name>
<name>
<surname><![CDATA[Friedman]]></surname>
<given-names><![CDATA[E.G.]]></given-names>
</name>
</person-group>
<source><![CDATA[Proceedings of the IEEE]]></source>
<year>2009</year>
<volume>97</volume>
<numero>1</numero>
<issue>1</issue>
<page-range>123-40</page-range></nlm-citation>
</ref>
<ref id="B24">
<nlm-citation citation-type="book">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Sait]]></surname>
<given-names><![CDATA[S.M.]]></given-names>
</name>
<name>
<surname><![CDATA[Youssef]]></surname>
<given-names><![CDATA[H.]]></given-names>
</name>
</person-group>
<source><![CDATA[Iterative computer algorithms with applications in engineering: Solving combinatorial optimization problems]]></source>
<year>1999</year>
<publisher-loc><![CDATA[California ]]></publisher-loc>
<publisher-name><![CDATA[IEEE Computer Society Press]]></publisher-name>
</nlm-citation>
</ref>
<ref id="B25">
<nlm-citation citation-type="">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Yang]]></surname>
<given-names><![CDATA[S.]]></given-names>
</name>
</person-group>
<source><![CDATA[Logic Synthesis and Optimization Benchmarks User Guide Version 3.0]]></source>
<year>1991</year>
</nlm-citation>
</ref>
<ref id="B26">
<nlm-citation citation-type="book">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Sait]]></surname>
<given-names><![CDATA[S.M.]]></given-names>
</name>
<name>
<surname><![CDATA[Youssef]]></surname>
<given-names><![CDATA[H.]]></given-names>
</name>
</person-group>
<source><![CDATA[VISI physical design automation: Theory and practice]]></source>
<year>1994</year>
<publisher-name><![CDATA[McGraw-Hill, Inc.]]></publisher-name>
</nlm-citation>
</ref>
<ref id="B27">
<nlm-citation citation-type="">
<article-title xml:lang=""><![CDATA[A software-supported methodology for designing high-performance 3D FPGA architectures]]></article-title>
<person-group person-group-type="author">
<name>
<surname><![CDATA[Siozios]]></surname>
<given-names><![CDATA[K.]]></given-names>
</name>
<name>
<surname><![CDATA[Sotiriadis]]></surname>
<given-names><![CDATA[K.]]></given-names>
</name>
<name>
<surname><![CDATA[Pavlidis]]></surname>
<given-names><![CDATA[V.F.]]></given-names>
</name>
<name>
<surname><![CDATA[Soudris]]></surname>
<given-names><![CDATA[D.]]></given-names>
</name>
</person-group>
<source><![CDATA[2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC]]></source>
<year>2007</year>
<page-range>54-9</page-range></nlm-citation>
</ref>
<ref id="B28">
<nlm-citation citation-type="journal">
<article-title xml:lang=""><![CDATA[Fuzzy sets]]></article-title>
<person-group person-group-type="author">
<name>
<surname><![CDATA[Zadeh]]></surname>
<given-names><![CDATA[L.a.]]></given-names>
</name>
</person-group>
<source><![CDATA[Information and Control]]></source>
<year>1965</year>
<volume>8</volume>
<numero>3</numero>
<issue>3</issue>
<page-range>338-53</page-range></nlm-citation>
</ref>
<ref id="B29">
<nlm-citation citation-type="journal">
<article-title xml:lang=""><![CDATA[Outline of a new approach to the analysis of complex systems and decision processes]]></article-title>
<person-group person-group-type="author">
<name>
<surname><![CDATA[Zadeh]]></surname>
<given-names><![CDATA[L.a.]]></given-names>
</name>
</person-group>
<source><![CDATA[IEEE Transactions on Systems, Man, and Cybernetics SMC]]></source>
<year>1973</year>
<volume>3</volume>
<page-range>28-44</page-range></nlm-citation>
</ref>
<ref id="B30">
<nlm-citation citation-type="journal">
<article-title xml:lang=""><![CDATA[The concept of a linguistic variable and its application to approximate reasoning-II]]></article-title>
<person-group person-group-type="author">
<name>
<surname><![CDATA[Zadeh]]></surname>
<given-names><![CDATA[L.A.]]></given-names>
</name>
</person-group>
<source><![CDATA[Information Sciences]]></source>
<year>1975</year>
<volume>8</volume>
<numero>4</numero>
<issue>4</issue>
<page-range>301-57</page-range></nlm-citation>
</ref>
</ref-list>
</back>
</article>
