Edwin Becerra–Álvarez*1, F. Sandoval–Ibarra2,3, José M– de la Rosa1
1 Instituto de Microelectrónica de Sevilla, IMSE–CNM (CSIC/University of Sevilla). Ed. CICA–CNM, Av. Reina Mercedes s/n, 41012 – Sevilla, SPAIN. *E–mail: jrosa@imse.com.es
2 CINVESTAV–Unidad Guadalajara. Av. Científica No. 1145, 45010, Col. El Bajío, Zapopan, Jalisco, MEXICO. *E–mail: Sandoval@cts–design.com
3 Mecatronics Engineering School, Universidad Panamericana–Campus Guadalajara, Zapopan 45010, JAL.
ABSTRACT
]]> This paper deals the design of a reconfigurable Low–Noise Amplifier (LNA) for the next generation of wireless hand–held devices by using a lumped circuit approach based on physical laws. The purpose is not only to present simulation results showing the fulfillment of different standard specifications, but also to demonstrate that each design step has a physical meaning such that the mathematical design flow is simple as well as suitable for hand–work in both laboratory and classroom. The circuit under analysis, which is designed according to technological design rules of a 90nm CMOS technology, is a two–stage topology including inductive–source degeneration, MOS–varactor based tuning networks, and programmable bias currents. This proposal, with reduced number of inductors and minimum power dissipation, adapts its performance to different standard specifications; the LNA is designed to cope with the requirements of GSM (PCS1900), WCDMA, Bluetooth and WLAN (IEEE 802.11b–g). In order to evaluate the effect of technology parasitics on the LNA performance, simulation results demonstrate that the LNA features NF<1.77dB, S21>16dB, S11<–5.5dB, S22<–5.5 dB and IIP3>–3.3 dBm over the 1.85–2.48 GHz band. For all the standards under study the adaptive power consumption varies from 25.3 mW to 53.3mW at a power supply of 1–V. The layout of the reconfigurable LNA occupies an area of 1.8mm2.Keywords: MOS Technology, wireless applications, reconfigurable circuits.
RESUMEN
Este trabajo presenta el diseño de un amplificador de bajo ruido, LNA (del inglés Low–Noise Amplifier) reconfigurable para la siguiente generación de dispositivos portátiles de comunicación inalámbricos, usando la aproximación de circuitos concentrados sustentada en leyes físicas. El propósito de este trabajo no es sólo presentar resultados de simulación que muestran el cumplimiento de especificaciones para cada estándar, sino también demostrar que cada paso de diseño tiene un significado físico haciendo que el procedimiento matemático de diseño sea simple y adecuado para el trabajo a mano tanto para actividades en laboratorio como en el aula. El circuito bajo análisis, diseñado en una tecnología CMOS 90nm, consta de dos etapas que incluyen degeneración inductiva de fuente, redes de entonado basadas en varactores MOS, y corrientes de polarización programables. Esta propuesta, con reducido número de inductores y mínima disipación de potencia, adapta su desempeño a las diversas especificaciones de cada estándar; el LNA se diseña para cubrir los requerimientos de GSM (PCS1900), WCDMA, Bluetooth y WLAN (IEEE 802.11b–g). Para evaluar el efecto de las no idealidades de la tecnología en el desempeño del LNA, las simulaciones demuestran que el circuito cumple parámetros como NF<1.77dB, S21>16dB, S11<–5.5dB, S22<–5.5 dB y IIP3>–3.3 dBm en la banda 1.85–2.48 GHz. Para todos los estándares bajo estudio, el consumo adaptivo de potencia varía de 25.3 mW a 53.3mW usando una fuente de alimentación de 1–V. El patrón geométrico del LNA reconfigurable consume un área de 1.8mm2.
Palabras clave: Tecnología MOS, aplicaciones inalámbricas, circuitos reconfigurables.
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