<?xml version="1.0" encoding="ISO-8859-1"?><article xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<front>
<journal-meta>
<journal-id>1665-6423</journal-id>
<journal-title><![CDATA[Journal of applied research and technology]]></journal-title>
<abbrev-journal-title><![CDATA[J. appl. res. technol]]></abbrev-journal-title>
<issn>1665-6423</issn>
<publisher>
<publisher-name><![CDATA[Universidad Nacional Autónoma de México, Instituto de Ciencias Aplicadas y Tecnología]]></publisher-name>
</publisher>
</journal-meta>
<article-meta>
<article-id>S1665-64232005000200007</article-id>
<title-group>
<article-title xml:lang="en"><![CDATA[Enhancing the symbolic analysis of analog circuits]]></article-title>
</title-group>
<contrib-group>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Tlelo-Cuautle]]></surname>
<given-names><![CDATA[E.]]></given-names>
</name>
<xref ref-type="aff" rid="A01"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Aguila-Meza]]></surname>
<given-names><![CDATA[J.]]></given-names>
</name>
</contrib>
</contrib-group>
<aff id="A01">
<institution><![CDATA[,Instituto Nacional de Astrofísica Optica y Electrónica Electronics Department ]]></institution>
<addr-line><![CDATA[Puebla ]]></addr-line>
<country>México</country>
</aff>
<pub-date pub-type="pub">
<day>00</day>
<month>00</month>
<year>2005</year>
</pub-date>
<pub-date pub-type="epub">
<day>00</day>
<month>00</month>
<year>2005</year>
</pub-date>
<volume>3</volume>
<numero>2</numero>
<fpage>150</fpage>
<lpage>160</lpage>
<copyright-statement/>
<copyright-year/>
<self-uri xlink:href="http://www.scielo.org.mx/scielo.php?script=sci_arttext&amp;pid=S1665-64232005000200007&amp;lng=en&amp;nrm=iso"></self-uri><self-uri xlink:href="http://www.scielo.org.mx/scielo.php?script=sci_abstract&amp;pid=S1665-64232005000200007&amp;lng=en&amp;nrm=iso"></self-uri><self-uri xlink:href="http://www.scielo.org.mx/scielo.php?script=sci_pdf&amp;pid=S1665-64232005000200007&amp;lng=en&amp;nrm=iso"></self-uri><abstract abstract-type="short" xml:lang="en"><p><![CDATA[A new symbolic-method is introduced to enhance the calculation of symbolic expressions of analog circuits. First, the analog circuit is transformed to a nullor equivalent circuit. Second, a new method is introduced to the formulation of a compact system of equations (CSEs). Third, a new method is introduced to the solution of the CSEs, by avoiding multiplications by zero to improve the evaluation of determinants. Finally, two examples are given to show the usefulness of the proposed methods to calculate fully symbolic transfer functions.]]></p></abstract>
<abstract abstract-type="short" xml:lang="es"><p><![CDATA[Se presenta un nuevo método simbólico para mejorar el cálculo de expresiones simbólicas de circuitos analógicos. En primer lugar, el circuito analógico es transformado a un circuito equivalente con anulador (nullor). Segundo, se presenta un nuevo método para la formulación de un sistema de ecuaciones compacto (SEC). Tercero, se presenta un nuevo método para la solución del SEC, evitando multiplicaciones por cero para mejorar la solución de determinantes. Finalmente, se presentan dos ejemplos para mostrar la utilidad de los métodos propuestos para calcular funciones de transferencia totalmente simbólicas.]]></p></abstract>
<kwd-group>
<kwd lng="en"><![CDATA[Circuit Theory]]></kwd>
<kwd lng="en"><![CDATA[Symbolic Analysis]]></kwd>
<kwd lng="en"><![CDATA[Nodal Analysis]]></kwd>
<kwd lng="en"><![CDATA[Operational Amplifier]]></kwd>
<kwd lng="en"><![CDATA[Operational Trans-Conductance Amplifier]]></kwd>
<kwd lng="en"><![CDATA[Nullor]]></kwd>
<kwd lng="en"><![CDATA[Cartesian Product]]></kwd>
<kwd lng="en"><![CDATA[Linear Algebra]]></kwd>
</kwd-group>
</article-meta>
</front><body><![CDATA[  	    <p align="center"><font face="verdana" size="4"><b>Enhancing the symbolic analysis of analog circuits</b></font></p>     <p align="center"><font face="verdana" size="4">&nbsp;</font></p> 	    <p align="center"><font face="verdana" size="2"><b>E. Tlelo&#45;Cuautle &amp; J. Aguila&#45;Meza</b></font></p>     <p align="center"><font face="verdana" size="2">&nbsp;</font></p>  	    <p align="justify"><font face="verdana" size="2"><i>INAOE, Department of Electronics. Instituto Tecnol&oacute;gico de Puebla. Puebla, Pue., M&eacute;xico.</i> <a href="mailto:etlelo@inaoep.mx">etlelo@inaoep.mx</a></font></p>     <p align="justify"><font face="verdana" size="2">&nbsp;</font></p>  	    <p align="justify"><font face="verdana" size="2">Received: February 2<sup>th</sup>, 2005.     <br>     Accepted: April 12<sup>th</sup> 2005.<i>    <br> 	</i></font></p> 	    ]]></body>
<body><![CDATA[<p align="justify"><font face="verdana" size="2">&nbsp;</font></p> 	    <p align="justify"><font face="verdana" size="2"> <b>Abstract</b></font></p>  	    <p align="justify"><font face="verdana" size="2">A new symbolic&#45;method is introduced to enhance the calculation of symbolic expressions of analog circuits. First, the analog circuit is transformed to a nullor equivalent circuit. Second, a new method is introduced to the formulation of a compact system of equations (CSEs). Third, a new method is introduced to the solution of the CSEs, by avoiding multiplications by zero to improve the evaluation of determinants. Finally, two examples are given to show the usefulness of the proposed methods to calculate fully symbolic transfer functions.</font></p> 	    <p align="justify"><font face="verdana" size="2"><b>Keywords:</b> Circuit Theory, Symbolic Analysis, Nodal Analysis, Operational Amplifier, Operational Trans&#45;Conductance Amplifier, Nullor, Cartesian Product, Linear Algebra.</font></p>     <p align="justify"><font face="verdana" size="2">&nbsp;</font></p>  	    <p align="justify"><font face="verdana" size="2"><b>Resumen</b></font></p>  	    <p align="justify"><font face="verdana" size="2">Se presenta un nuevo m&eacute;todo simb&oacute;lico para mejorar el c&aacute;lculo de expresiones simb&oacute;licas de circuitos anal&oacute;gicos. En primer lugar, el circuito anal&oacute;gico es transformado a un circuito equivalente con anulador (nullor). Segundo, se presenta un nuevo m&eacute;todo para la formulaci&oacute;n de un sistema de ecuaciones compacto (SEC). Tercero, se presenta un nuevo m&eacute;todo para la soluci&oacute;n del SEC, evitando multiplicaciones por cero para mejorar la soluci&oacute;n de determinantes. Finalmente, se presentan dos ejemplos para mostrar la utilidad de los m&eacute;todos propuestos para calcular funciones de transferencia totalmente simb&oacute;licas.</font></p>     <p align="justify">&nbsp;	</p> 	    <p align="justify"><font size="2" face="verdana"><a href="../pdf/jart/v3n2/v3n2a7.pdf" target="_blank">DESCARGAR ART&Iacute;CULO EN FORMATO PDF</a></font></p> 	    <p align="justify"><font face="verdana" size="2">&nbsp;</font></p>     ]]></body>
<body><![CDATA[<p align="justify"><font face="verdana" size="2"><b>ACKNOWLEDGMENT</b></font></p>         <p align="justify"><font face="verdana" size="2">This work has been partially supported by CoSNET/MEXICO, under the project number 454.03&#45;p.</font></p>     <p align="justify">&nbsp;</p>         <p align="justify"><font face="verdana" size="2"><b>REFERENCES</b></font></p>         <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;1&#93; Chua. L. O. and Lin P.M., Computer&#45;Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques, NJ: Prentlce&#45;Hall, 1975.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4817252&pid=S1665-6423200500020000700001&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>         <!-- ref --><p align="justify"><font face="verdana" size="2"> &#91;2&#93; Lin P.M., Studies in Electrical and Electronic Engineering 41: Symbolic Network Analysis, New York: Elsevier, 1991.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4817254&pid=S1665-6423200500020000700002&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>         <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;3&#93; Fern&aacute;ndez, F. V. Symbolic Analysis Techniques. In Applications to Analog Design Automation. The IEEE PRESS, Inc., New York 1998.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4817256&pid=S1665-6423200500020000700003&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     ]]></body>
<body><![CDATA[<!-- ref --><p align="justify"><font face="verdana" size="2">&#91;4&#93; Rutenbar R. A., Gielen G. and Antao B. A., Computer&#45;Aided Design of Analog Integrated Circuits and Systems, NJ: IEEE Press, 2002.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4817258&pid=S1665-6423200500020000700004&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;5&#93; Toumazou C., Moschytz G. and Barrie G., Trade&#45;offs in analog circuit design, The Netherlands: Kluwer, 2002.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4817260&pid=S1665-6423200500020000700005&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;6&#93; Gielen G., Wambacq P., Sansen W.M., Symbolic analysis methods and applications for analog tutorial overview, Proceedings of the IEEE, vol. 82. no. 2. pp. 287&#45;304,  February 1994.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4817262&pid=S1665-6423200500020000700006&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2"> &#91;7&#93; Hassoun M. M., Pen&#45;Min L., A hierarchical network approach to symbolic analysls of large&#45;scale network. Transactions on Circuits and Systems&#45;I, vol. 42, no. 4, pp. 201&#45;211, 1995.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4817264&pid=S1665-6423200500020000700007&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <p align="justify"><font face="verdana" size="2"> &#91;8&#93; H. Schmld, Approximating the universal active element, IEEE transactions on Circuits and Systems&#45;I no. 11, pp. 1160&#45;1169, November 2000.</font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2"> &#91;9&#93; J. A. Svoboda, Using nullors to analyze linear networks, Circuit Theory and applications, vol. 14. pp. 1986.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4817267&pid=S1665-6423200500020000700008&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>         <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;10&#93; Floberg H. Symbolic analysis in analog integrated circuit design, Norwell, Ma.  Kluwer, 1997.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4817269&pid=S1665-6423200500020000700009&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;11&#93; Tlelo&#45;Cuautle E., Sarmiento&#45;Reyes A., A pure nodal analysis method suitable for analog circuits, with the Journal of Applied Research and Technology, vol. 1, no 3. pp. 235&#45;247 October 2003.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4817271&pid=S1665-6423200500020000700010&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>         <p align="justify"><font face="verdana" size="2">&#91;12&#93; E. Tlelo&#45;Cuautle, et al., SIASCA Interactive system for the symbolic analysis of analog circuits IEICE Express, vol. 1, no. 1, pp. 19&#45;23, April 2004.</font></p>         <!-- ref --><p align="justify"><font face="verdana" size="2"> &#91;13&#93; C.J. Richard Shi and Xiang&#45;Dong Tan, Canonical symbolic analysis of large analog circuits with del decision diagrams, IEEE Transactions on Computer&#45;Aided Design, vol. 19, no.1, pp. 1<b>&#45;</b>18, January 2000.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4817274&pid=S1665-6423200500020000700011&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>         <p align="justify"><font face="verdana" size="2">&#91;14&#93; W. Verhaegen, G. Gielen, Efficient DDD&#45;Based Symbolic Analysis of Linear Analog Circuits IEEE Circuits and Systems&#45;ll, vol. 49, no. 7, pp. 474&#45;487, July 2002. </font></p>         <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;15&#93; Sheldon X.&#45;D. Tan, C.&#45;J. Richard Shi, Efficient approximation of symbolic expressions for analog  modeling and analysis, IEEE Transactions on Computer&#45;Aided Design, vol. 23, no. 6, pp. 907-918, 200.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4817277&pid=S1665-6423200500020000700012&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --> </font></p>         <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;16&#93; Ahmad M. Ibrahim, Introduction to applied fuzzy electronics, NJ: Prentice&#45;Hall, 1997.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4817279&pid=S1665-6423200500020000700013&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --> </font></p>         <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;17&#93; Randall L.G., S&aacute;nchez&#45;Sinencio E., Active Filter Design Using Operational Transconductance An Tutorial, IEEE Circuits and Devices Magazine, pp. 20&#45;32, 1985.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4817281&pid=S1665-6423200500020000700014&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --> </font></p>         <p align="justify"><font face="verdana" size="2">&#91;18&#93; E. Tlelo&#45;Cuautle, C. S&aacute;nchez&#45;L&oacute;pez, Symbolic computation of NF of transistor circuits, IEICE Trans, Fundamentals of Electronics, Communications and Computer Sciences, vol. E87&#45;A, no. 9, pp. September 2004.</font></p>     <p align="justify">&nbsp;</p>         <p align="justify"><font face="verdana" size="2"><b>Authors Biography</b></font></p>         <p align="justify"><font face="verdana" size="2"><b>Esteban Tlelo&#45;Cuautle.</b> received the B.Sc. degree in Electronics Engineering from the Ted Institute of Puebla <i>(Instituto Tecnol&oacute;gico de Puebla),</i> M&eacute;xico, in 1993, the M.Sc. and Ph.D. degrees from the Institute for Astrophysics, Optics and Electronics (INAOE), M&eacute;xico, in 1995 and 2000, respectively. Since Jan he has been with the Electronics Department at INAOE, where he is currently a Researcher. He is Senior M the IEEE, and his research interests include analog design automation, modeling and simulation of nonlinear circuits, symbolic analysis, circuit synthesis, and analog and mixed&#45;signal CAD tools.</font></p>         <p align="justify"><font face="verdana" size="2"><b>Jorge Aguila&#45;Meza.</b> received the B.Sc. degree In Electronics from the <i>Benem&eacute;rita Universidad Aut&oacute;noma de Puebla</i> (BUAP), M&eacute;xico, in 2003, and the M.Sc. degree from the National Institule for Astrophysics, Optics and Electronics (INAOE), M&eacute;xico, in 2004. His research interests include analog CAD tools, symbol analysis, modelling and simulation of analog integrated circuits.</font></p>     ]]></body>
<body><![CDATA[ ]]></body><back>
<ref-list>
<ref id="B1">
<label>1</label><nlm-citation citation-type="book">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Chua]]></surname>
<given-names><![CDATA[L. O.]]></given-names>
</name>
<name>
<surname><![CDATA[Lin]]></surname>
<given-names><![CDATA[P.M.]]></given-names>
</name>
</person-group>
<source><![CDATA[Computer-Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques]]></source>
<year>1975</year>
<publisher-loc><![CDATA[NJ ]]></publisher-loc>
<publisher-name><![CDATA[Prentlce-Hall]]></publisher-name>
</nlm-citation>
</ref>
<ref id="B2">
<label>2</label><nlm-citation citation-type="book">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Lin]]></surname>
<given-names><![CDATA[P.M.]]></given-names>
</name>
</person-group>
<source><![CDATA[Symbolic Network Analysis]]></source>
<year>1991</year>
<volume>41</volume>
<publisher-loc><![CDATA[New York ]]></publisher-loc>
<publisher-name><![CDATA[Elsevier]]></publisher-name>
</nlm-citation>
</ref>
<ref id="B3">
<label>3</label><nlm-citation citation-type="book">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Fernández]]></surname>
<given-names><![CDATA[F. V.]]></given-names>
</name>
</person-group>
<source><![CDATA[Symbolic Analysis Techniques. In Applications to Analog Design Automation]]></source>
<year>1998</year>
<publisher-loc><![CDATA[New York ]]></publisher-loc>
<publisher-name><![CDATA[The IEEE PRESS, Inc.]]></publisher-name>
</nlm-citation>
</ref>
<ref id="B4">
<label>4</label><nlm-citation citation-type="book">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Rutenbar]]></surname>
<given-names><![CDATA[R. A.]]></given-names>
</name>
<name>
<surname><![CDATA[Gielen]]></surname>
<given-names><![CDATA[G.]]></given-names>
</name>
<name>
<surname><![CDATA[Antao]]></surname>
<given-names><![CDATA[B. A.]]></given-names>
</name>
</person-group>
<source><![CDATA[Computer-Aided Design of Analog Integrated Circuits and Systems]]></source>
<year>2002</year>
<publisher-loc><![CDATA[NJ ]]></publisher-loc>
<publisher-name><![CDATA[IEEE Press]]></publisher-name>
</nlm-citation>
</ref>
<ref id="B5">
<label>5</label><nlm-citation citation-type="book">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Toumazou]]></surname>
<given-names><![CDATA[C.]]></given-names>
</name>
<name>
<surname><![CDATA[Moschytz]]></surname>
<given-names><![CDATA[G.]]></given-names>
</name>
<name>
<surname><![CDATA[Barrie]]></surname>
<given-names><![CDATA[G.]]></given-names>
</name>
</person-group>
<source><![CDATA[Trade-offs in analog circuit design]]></source>
<year>2002</year>
<publisher-name><![CDATA[Kluwer]]></publisher-name>
</nlm-citation>
</ref>
<ref id="B6">
<label>6</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Gielen]]></surname>
<given-names><![CDATA[G.]]></given-names>
</name>
<name>
<surname><![CDATA[Wambacq]]></surname>
<given-names><![CDATA[P.]]></given-names>
</name>
<name>
<surname><![CDATA[Sansen]]></surname>
<given-names><![CDATA[W.M.]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Symbolic analysis methods and applications for analog tutorial overview]]></article-title>
<source><![CDATA[Proceedings of the IEEE]]></source>
<year>Febr</year>
<month>ua</month>
<day>ry</day>
<volume>82</volume>
<numero>2</numero>
<issue>2</issue>
<page-range>287-304</page-range></nlm-citation>
</ref>
<ref id="B7">
<label>7</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Hassoun]]></surname>
<given-names><![CDATA[M. M.]]></given-names>
</name>
<name>
<surname><![CDATA[Pen-Min]]></surname>
<given-names><![CDATA[L.]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[A hierarchical network approach to symbolic analysls of large-scale network]]></article-title>
<source><![CDATA[Transactions on Circuits and Systems-I]]></source>
<year>1995</year>
<volume>42</volume>
<numero>4</numero>
<issue>4</issue>
<page-range>201-211</page-range></nlm-citation>
</ref>
<ref id="B8">
<label>9</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Svoboda]]></surname>
<given-names><![CDATA[J. A.]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Using nullors to analyze linear networks]]></article-title>
<source><![CDATA[Circuit Theory and applications]]></source>
<year>1986</year>
<volume>14</volume>
</nlm-citation>
</ref>
<ref id="B9">
<label>10</label><nlm-citation citation-type="book">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Floberg]]></surname>
<given-names><![CDATA[H.]]></given-names>
</name>
</person-group>
<source><![CDATA[Symbolic analysis in analog integrated circuit design]]></source>
<year>1997</year>
<publisher-loc><![CDATA[Norwell^eMa. Ma.]]></publisher-loc>
<publisher-name><![CDATA[Kluwer]]></publisher-name>
</nlm-citation>
</ref>
<ref id="B10">
<label>11</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Tlelo-Cuautle]]></surname>
<given-names><![CDATA[E.]]></given-names>
</name>
<name>
<surname><![CDATA[Sarmiento-Reyes]]></surname>
<given-names><![CDATA[A.]]></given-names>
</name>
</person-group>
<source><![CDATA[Journal of Applied Research and Technology]]></source>
<year>Octo</year>
<month>be</month>
<day>r </day>
<volume>1</volume>
<numero>3</numero>
<issue>3</issue>
<page-range>235-247</page-range></nlm-citation>
</ref>
<ref id="B11">
<label>13</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Shi]]></surname>
<given-names><![CDATA[C.J. Richard]]></given-names>
</name>
<name>
<surname><![CDATA[Tan]]></surname>
<given-names><![CDATA[Xiang-Dong]]></given-names>
</name>
</person-group>
<source><![CDATA[IEEE Transactions on Computer-Aided Design]]></source>
<year>Janu</year>
<month>ar</month>
<day>y </day>
<volume>19</volume>
<numero>1</numero>
<issue>1</issue>
<page-range>1-18</page-range></nlm-citation>
</ref>
<ref id="B12">
<label>15</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Tan]]></surname>
<given-names><![CDATA[Sheldon X.-D.]]></given-names>
</name>
<name>
<surname><![CDATA[Shi]]></surname>
<given-names><![CDATA[C.-J. Richard]]></given-names>
</name>
</person-group>
<source><![CDATA[IEEE Transactions on Computer-Aided Design]]></source>
<year></year>
<volume>23</volume>
<numero>6</numero>
<issue>6</issue>
<page-range>907-918</page-range></nlm-citation>
</ref>
<ref id="B13">
<label>16</label><nlm-citation citation-type="book">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Ahmad]]></surname>
<given-names><![CDATA[M. Ibrahim]]></given-names>
</name>
</person-group>
<source><![CDATA[Introduction to applied fuzzy electronics]]></source>
<year>1997</year>
<publisher-loc><![CDATA[NJ ]]></publisher-loc>
<publisher-name><![CDATA[Prentice-Hall]]></publisher-name>
</nlm-citation>
</ref>
<ref id="B14">
<label>17</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Randall]]></surname>
<given-names><![CDATA[L.G.]]></given-names>
</name>
<name>
<surname><![CDATA[Sánchez-Sinencio]]></surname>
<given-names><![CDATA[E.]]></given-names>
</name>
</person-group>
<source><![CDATA[IEEE Circuits and Devices Magazine]]></source>
<year>1985</year>
<page-range>20-32</page-range></nlm-citation>
</ref>
</ref-list>
</back>
</article>
