Sistema Híbrido Hardware/Software para el Entrenamiento de Redes SOFM

Agustín Ramírez Agundis¹, Rafael Gadea Girones², Ricardo Colom Palero² and Javier Díaz Carmona¹

¹ Department of Electronic Engineering, Instituto Tecnológico de Celaya, Av. Tecnológico s/n; 38010; Celaya, Gto., México; E–mails: aagundis@itc.mx, jdiaz@itc.mx

² Department of Electronic Engineering, Universidad Politecnica de Valencia, Camino de Vera s/n, 46020; Valencia, Spain; E–mails: rgadea@eln.upv.es, rcolom@eln.upv.es

Article received on August 31, 2007 ]]> Accepted on November 30, 2007

Abstract

This paper describes the design of a training system for a Self–Organizing Feature Map (SOFM). The system design aims two goals. The first is to reduce the training processing time by exploiting the inherent neural networks (NNs) parallelism through the SOFM hardware implementation. The second goal is to provide versatility to the training process by means of pre– and post processing of input and output data using Matlab–Simulink, which is also used as the software platform. The system uses as a coprocessor an FPGA based board connected via PCI bus at the host PC. To illustrate the system functionality we developed an application to analyze the effects over the map of scattering size in randomly generated weight initial values. When compared with the software approach for the same application, our system reduces the training time in 89%.

Keywords: Self Organizing Feature Map, Mixed Hardware/Software Implementation, Field Programmable Gate Array, Neural coprocessor.

Resumen

Este artículo describe un sistema para entrenar una red neuronal Self–Organizing Feature Map (SOFM). El diseño del sistema persigue dos objetivos. Primero, reducir el tiempo de procesamiento requerido para entrenar la red sacando provecho del paralelismo intrínseco de las redes neurona–les mediante la implementación hardware de la SOFM. Segundo: proporcionar versatilidad al entrenamiento por medio del pre y post procesamiento de los datos de entrada usando Matlab–Simulink, también utilizado como plataforma del software. El sistema usa como coprocesador una tarjeta basada en un FPGA conectada a la PC anfitriona a través del bus PCI. Para ilustrar la funcionalidad del sistema se desarrolló una aplicación para analizar los efectos que sobre el mapeo tiene el tamaño de la dispersión de los valores iniciales de los pesos generados aleatoriamente. Cuando se compara con un sistema totalmente software para la misma aplicación, nuestro sistema reduce el tiempo de entrenamiento en 89%.

Palabras clave: Mapeo de rasgos auto–organizado, Implementación híbrida hardware/software, Arreglo de compuertas programables en campo, Coprocesador neuronal.

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