Exposing Instruction Level Parallelism in the Presence of Loops
Exponiendo el Paralelismo a Nivel de Instrucciones en Presencia de Bucles
Graduated: Marcos R. de Alba
Department of Electrical and Computer Engineering
Northeastern University
Boston MA 02115 ]]>
e–mail: mdealba@ece.neu.edu
Advisor: Dr. David Kaeli
Computer Architecture Research Laboratory (NUCAR)
Northeastern University
Boston MA 02115
Graduated on May 1, 2004
Abstract
In this thesis we explore how to utilize a loop cache to relieve the unnecessary pressure placed on the trace cache by loops. Due to the high temporal locality of loops, loops should be cached. We have observed that when loops contain control flow instructions in their bodies it is better to collect traces on a dedicated loop cache instead of using trace cache space. The traces of instructions within loops tend to exhibit predictable patterns that can be detected and exploited at run–time. We propose to capture dynamic traces of loop bodies in a loop cache. The novelty of this loop cache consists of dynamically capturing loop iterations with conditional branches and correlating them to unique loops. Once loop iterations are cached in the loop cache, their bodies can be provided by the loop cache without polluting the trace cache and without any instruction cache accesses. The proposed loop cache includes hardware capable of dynamically unfolding loops such that large traces of instructions are accessed in a single loop cache interrogation.
]]> We evaluate our loop cache and compare it against a baseline machine with a larger first–level instruction cache. We also consider how the loop cache can compliment the introduction of a trace cache by filtering out loop traces that needlessly dominate the trace cache space. We quantify the benefits provided by a fetch engine equipped with the proposed loop cache and unrolling hardware. In our experiments we explore the design space of a loop cache and associated unfolding hardware and evaluate its efficiency to detect independent iterations in loops in SPECint2000, Media–Bench and MiBench applications. We show that trace cache efficiency and ILP can be significantly improved using our loop caching scheme. This improvement translates into up to 38% performance speedup when compared to a baseline machine with a loop cache and no trace cache to a baseline machine with no loop cache. Further experiments show up to a 16% speedup on a hybrid machine with loop and trace cache compared to a machine with a larger 1 cache and a trace cache.
Resumen
Este trabajo se concentra en el análisis y detección de bucles para incrementar el paralelismo a nivel de instrucciones a través de la especulación de visitas enteras a los bucles. En la tesis se comparan las técnicas propuestas con otras existentes y se proponen técnicas híbridas que explotan las características benéficas de los mecanismos involucrados. Se lleva a cabo un estudio dinámico de las propiedades de muchos conjuntos de aplicaciones con el fin de determinar las características óptimas del hardware propuesto. Tal incluye una memoria cache especialmente diseñada para el almacenamiento y manejo óptimo de instrucciones pertenecientes a los bucles. Proveyendo miles de instrucciones para especulación en la memoria cache de bucles se obtienen aceleraciones en la mayoría de las aplicaciones con el mismo presupuesto de hardware. Se presenta de forma detallada el estudio exhaustivo de técnicas similares así como los detalles del diseño del hardware propuesto. Se justifican cada una de las características basadas en estudios dinámicos de las propiedades de las aplicaciones. También se analizan posibles formas de proveer mayor ganancia en el rendimiento y se presentan alternativas de adaptación del hardware en arquitecturas futuras y en procesadores comerciales existentes.
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