<?xml version="1.0" encoding="ISO-8859-1"?><article xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<front>
<journal-meta>
<journal-id>1665-6423</journal-id>
<journal-title><![CDATA[Journal of applied research and technology]]></journal-title>
<abbrev-journal-title><![CDATA[J. appl. res. technol]]></abbrev-journal-title>
<issn>1665-6423</issn>
<publisher>
<publisher-name><![CDATA[Universidad Nacional Autónoma de México, Instituto de Ciencias Aplicadas y Tecnología]]></publisher-name>
</publisher>
</journal-meta>
<article-meta>
<article-id>S1665-64232015000500483</article-id>
<article-id pub-id-type="doi">10.1016/j.jart.2015.10.004</article-id>
<title-group>
<article-title xml:lang="en"><![CDATA[Characterization and synthesis of a 32-bit asynchronous microprocessor in synchronous reconfigurable devices]]></article-title>
</title-group>
<contrib-group>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Pedroza de la Crúz]]></surname>
<given-names><![CDATA[Adrian]]></given-names>
</name>
<xref ref-type="aff" rid="Aff"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Reyes Barón]]></surname>
<given-names><![CDATA[José Roberto]]></given-names>
</name>
<xref ref-type="aff" rid="Aff"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Ortega Cisneros]]></surname>
<given-names><![CDATA[Susana]]></given-names>
</name>
<xref ref-type="aff" rid="Aff"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Raygoza Panduro]]></surname>
<given-names><![CDATA[Juan José]]></given-names>
</name>
<xref ref-type="aff" rid="Aff"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Carrazco Díaz]]></surname>
<given-names><![CDATA[Miguel Ángel]]></given-names>
</name>
<xref ref-type="aff" rid="Aff"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Loo Yau]]></surname>
<given-names><![CDATA[José Raúl]]></given-names>
</name>
<xref ref-type="aff" rid="Aff"/>
</contrib>
</contrib-group>
<aff id="Af1">
<institution><![CDATA[,Instituto Politécnico Nacional Unidad Guadalajara Centro de Investigación y Estudios Avanzados]]></institution>
<addr-line><![CDATA[Zapopan Jalisco]]></addr-line>
<country>MX</country>
</aff>
<aff id="Af2">
<institution><![CDATA[,Universidad de Guadalajara Centro Universitario de Ciencias Exactas, e Ingenierías ]]></institution>
<addr-line><![CDATA[Guadalajara Jalisco]]></addr-line>
<country>MX</country>
</aff>
<pub-date pub-type="pub">
<day>00</day>
<month>00</month>
<year>2015</year>
</pub-date>
<pub-date pub-type="epub">
<day>00</day>
<month>00</month>
<year>2015</year>
</pub-date>
<volume>13</volume>
<numero>5</numero>
<fpage>483</fpage>
<lpage>497</lpage>
<copyright-statement/>
<copyright-year/>
<self-uri xlink:href="http://www.scielo.org.mx/scielo.php?script=sci_arttext&amp;pid=S1665-64232015000500483&amp;lng=en&amp;nrm=iso"></self-uri><self-uri xlink:href="http://www.scielo.org.mx/scielo.php?script=sci_abstract&amp;pid=S1665-64232015000500483&amp;lng=en&amp;nrm=iso"></self-uri><self-uri xlink:href="http://www.scielo.org.mx/scielo.php?script=sci_pdf&amp;pid=S1665-64232015000500483&amp;lng=en&amp;nrm=iso"></self-uri><abstract abstract-type="short" xml:lang="en"><p><![CDATA[This paper presents the design, implementation, and experimental results of 32-bit asynchronous microprocessor developed in a synchronous reconfigurable device (FPGA), taking advantage of a hard macro. It has support for floating point operations, such as addition, subtraction, and multiplication, and is based on the IEEE 754-2008 standard with 32-bit simple precision. This work describes the different blocks of the microprocessors as delay modules, needed to implement a Self-Timed (ST) protocol in a synchronous system, and the operational analysis of the asynchronous central unit, according to the developed occupations and speeds. The ST control is based on a micropipeline used as a centralized generator of activation signals that permit the performance of the operations in the microprocessor without the need of a global clock. This work compares the asynchronous microprocessor with a synchronous version. The parameters evaluated are power consumption, area, and speed. Both circuits were designed and implemented in an FPGA Virtex 5. The performance obtained was 4 MIPS for the asynchronous microprocessor against 1.6 MIPS for the synchronous.]]></p></abstract>
<kwd-group>
<kwd lng="en"><![CDATA[Asynchronous]]></kwd>
<kwd lng="en"><![CDATA[Microprocessor]]></kwd>
<kwd lng="en"><![CDATA[Floating point]]></kwd>
<kwd lng="en"><![CDATA[FPGA delay macro]]></kwd>
<kwd lng="en"><![CDATA[Real time]]></kwd>
</kwd-group>
</article-meta>
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