H. J. Saavedra-Gómez¹, J. R. Loo-Yau¹, Juan Luis del Valle-Padilla¹, P. Moreno¹ , F. Sandoval-lbarra*¹ and J.A. Reynoso-Hernández²

¹ Centro de Investigación y de Estudios Avanzados del l. P. N. Unidad Guadalajara, Av. del Bosque 1145, Colonia El Bajío, C. P. 45037, Zapopan Jalisco, México.

² Centro de Investigación Científica y de Educación Superior de Ensenada, Carretera Ensenada-Tijuana 3918, Zona Playitas, C. P. 22860, Ensenada, B. C., México. sandoval@cts_desing.com

ABSTRACT

In this work a technique to heighten the breakdown voltage and the transition frequency (f_T) in standard MOS technology is presented. By using an optimized extended drift region at the drain, a CMOS FET can achieve higher breakdown voltage. To enhance the operation frequency, the standard analog/digital pads were modified to decrease coupling effects with the substrate. These two enhancements make the proposed MOSFET structure suitable for mid-power RF applications. Experimental measurements on a High Voltage MOSFET (HVMOS FET) show a breakdown voltage of 20 V, IP3 of +30.2 dBm and an improvement of 31.9% and 34.7% of the extrinsic f_T and f_max, respectively.

RESUMEN

Se presenta una técnica para incrementar el voltaje de ruptura y la frecuencia de transición en dispositivos MOSFET fabricados en una tecnología CMOS estándar (0.5 μm, 5V). Colocando una región de arrastre extendida sobre el drenador, el MOSFET puede alcanzar un mayor voltaje de ruptura. Para mejorar la frecuencia de operación, se modificaron los pads analógico/digital para minimizar el acoplamiento que puede existir hacia el substrato. Ambas mejoras hacen que la estructura propuesta del MOSFET sea adecuada para aplicaciones RF de potencia media. Los resultados experimentales muestran un voltaje de ruptura de 20 V, una IP3 de +30.2 dBm y una mejora del 31.9% y 34.7% en las frecuencias f_T y f_max, respectivamente.

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References

[1] A. Tombak, "Highly Integrated Wireless Handset Front-End Modules Based on Bulk Silicon and Silicon-on-Insulator (SOI) Technologies," IMS Workshop WSF, Boston 2009.         [ Links ]

[2] John Pritiskutch-Brett Hanson, "Understanding LDMOS Device Fundamentals, ST Application Note AN1226" (On Line), http://www.rfdh.com/ez/system/db/lib_app/upload/283/[STM]_UNDERSTANDING_LDMOS_DEVICE_FUNDAMENTALS.pdf.         [ Links ]

[3] I. Aoki, S. Kee, D. Rutledge, and A. Hajimiri, "Fully-Integrated CMOS Power Amplifier Design Using the Distributed Active Transformer Architecture," IEEE J. Solid-state Circuits, Vol. 37, No. 3, pp 371-383, Mar. 2002.         [ Links ]

[4] A.W. Ludikhuize, A Review of RESURF Technology, in Proceedings of 12th International Symposium on Power Semiconductor Devices & ICs, 2000, pp. 11-18.         [ Links ]

[5] Juan Isdriel Urias Mesa, "Transistor de Alto Voltaje en Tecnologia CMOS Estandar", Master of Science Thesis in Electrical Engineering, CINVESTAV Guadalajara, Nov. 2003.         [ Links ]

[6] Jyh-Chyurn Guo, Yi-Hsiu Tsai, " A Broadband and Scalable Lossy Substrate Model for RF Noise Simulation and Analysis in Nanoscale MOSFETs With Various Pad Structures," IEEE Transactions on Microwave Theory and Techniques, Vol. 57, No. 2, pp. 271-281, February 2009.         [ Links ]

[7] J. Cheng, S. Li, B. Han, J. Gao," Analysis and modeling of the pads for RF CMOS Based on EM Simulation," Microwave Journal, Vol. 53, No 10, p. 96, October 2010.         [ Links ]

[8] Adem Aktas, Mohammed Ismail, "Pad De-Embedding in RF-CMOS," IEEE Circuit & Devices Magazine, Vol. 17, No 3, pp. 88-11, May 2001.         [ Links ]