<?xml version="1.0" encoding="ISO-8859-1"?><article xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<front>
<journal-meta>
<journal-id>1665-6423</journal-id>
<journal-title><![CDATA[Journal of applied research and technology]]></journal-title>
<abbrev-journal-title><![CDATA[J. appl. res. technol]]></abbrev-journal-title>
<issn>1665-6423</issn>
<publisher>
<publisher-name><![CDATA[Universidad Nacional Autónoma de México, Instituto de Ciencias Aplicadas y Tecnología]]></publisher-name>
</publisher>
</journal-meta>
<article-meta>
<article-id>S1665-64232011000100006</article-id>
<title-group>
<article-title xml:lang="en"><![CDATA[Symbolic Analysis of OTRAs-Based Circuits]]></article-title>
</title-group>
<contrib-group>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Sánchez-López]]></surname>
<given-names><![CDATA[C]]></given-names>
</name>
<xref ref-type="aff" rid="A01"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Martínez-Romero]]></surname>
<given-names><![CDATA[E]]></given-names>
</name>
<xref ref-type="aff" rid="A03"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Tlelo-Cuautle]]></surname>
<given-names><![CDATA[E]]></given-names>
</name>
<xref ref-type="aff" rid="A03"/>
</contrib>
</contrib-group>
<aff id="A01">
<institution><![CDATA[,Universidad Autónoma de Tamaulipas Department of Electronics ]]></institution>
<addr-line><![CDATA[Apizaco Tlaxcala]]></addr-line>
<country>Mexico</country>
</aff>
<aff id="A02">
<institution><![CDATA[,University of Seville Instituto de Microelectrónica de Sevilla Centro Nacional de Microelectrónica]]></institution>
<addr-line><![CDATA[Sevilla ]]></addr-line>
</aff>
<aff id="A03">
<institution><![CDATA[,Instituto Nacional de Astrofísica, Óptica y Electrónica Department of Electronics ]]></institution>
<addr-line><![CDATA[Tonantzintla Puebla]]></addr-line>
</aff>
<pub-date pub-type="pub">
<day>00</day>
<month>04</month>
<year>2011</year>
</pub-date>
<pub-date pub-type="epub">
<day>00</day>
<month>04</month>
<year>2011</year>
</pub-date>
<volume>9</volume>
<numero>1</numero>
<fpage>69</fpage>
<lpage>80</lpage>
<copyright-statement/>
<copyright-year/>
<self-uri xlink:href="http://www.scielo.org.mx/scielo.php?script=sci_arttext&amp;pid=S1665-64232011000100006&amp;lng=en&amp;nrm=iso"></self-uri><self-uri xlink:href="http://www.scielo.org.mx/scielo.php?script=sci_abstract&amp;pid=S1665-64232011000100006&amp;lng=en&amp;nrm=iso"></self-uri><self-uri xlink:href="http://www.scielo.org.mx/scielo.php?script=sci_pdf&amp;pid=S1665-64232011000100006&amp;lng=en&amp;nrm=iso"></self-uri><abstract abstract-type="short" xml:lang="en"><p><![CDATA[A new nullor-based model to describe the behavior of Operational Transresistance Amplifiers (OTRAs) is introduced. The new model is composed of four nullors and three grounded resistors. As a consequence, standard nodal analysis can be applied to compute fully-symbolic small-signal characteristics of OTRA-based analog circuits, and the nullor-based OTRAs model can be used in CAD tools. In this manner, the fully-symbolic transfer functions of several application circuits, such as filters and oscillators can easily be approximated.]]></p></abstract>
<abstract abstract-type="short" xml:lang="es"><p><![CDATA[En el presente trabajo se presenta un nuevo modelo basado en nullors para describir el comportamiento de amplificadores operacionales de transresistencia (OTRAs). El modelo se compone de cuatro nullors y tres resistores aterrizados; como resultado, se puede aplicar el análisis nodal estándar para calcular características de pequeña señal completamente simbólicas de circuitos analógicos basados en OTRAs; este nuevo modelo puede ser usado en herramientas CAD. De esta forma, las funciones de transferencia completamente simbólica de varios circuitos de aplicación tales como filtros y osciladores, pueden aproximarse fácilmente.]]></p></abstract>
<kwd-group>
<kwd lng="en"><![CDATA[Operational Transresistance Amplifier]]></kwd>
<kwd lng="en"><![CDATA[nullor]]></kwd>
<kwd lng="en"><![CDATA[nodal analysis]]></kwd>
</kwd-group>
</article-meta>
</front><body><![CDATA[ <p align="center"><font face="verdana" size="4"><b>Symbolic Analysis of OTRAs&#150;Based Circuits</b></font></p>     <p align="center"><font face="verdana" size="2">&nbsp;</font></p>     <p align="center"><font face="verdana" size="2"><b>C. S&aacute;nchez&#150;L&oacute;pez*<sup>1,2</sup>, E. Mart&iacute;nez&#150;Romero<sup>3</sup>, E. Tlelo&#150;Cuautle<sup>3</sup></b></font></p>     <p align="justify"><font face="verdana" size="2">&nbsp;</font></p>     <p align="justify"><font face="verdana" size="2"><i><sup>1</sup> Department of Electronics, UAT, Mexico, Czda Apizaquito s/n, Apizaco, Tlaxcala, 140. *E&#150;mail:</i> <a href="mailto:carlsanmx@yahoo.com.mx">carlsanmx@yahoo.com.mx</a></font></p>     <p align="justify"><font face="verdana" size="2"><i><sup>2</sup> IMSE&#150;CNM, CSIC and University of Seville, Spain, Avda. Americo Vespucio s/n, Isla de la Cartuja, Sevilla, 41090.</i></font></p>     <p align="justify"><font face="verdana" size="2"><i><sup>3</sup> Department of Electronics, INAOE, Mexico, Luis Enrique Erro No. 1 Tonantzintla, Puebla, 72840.</i></font></p>     <p align="justify"><font face="verdana" size="2">&nbsp;</font></p>     <p align="justify"><font face="verdana" size="2"><b>ABSTRACT</b></font></p>     <p align="justify"><font face="verdana" size="2">A new nullor&#150;based model to describe the behavior of Operational Transresistance Amplifiers (OTRAs) is introduced. The new model is composed of four nullors and three grounded resistors. As a consequence, standard nodal analysis can be applied to compute fully&#150;symbolic small&#150;signal characteristics of OTRA&#150;based analog circuits, and the nullor&#150;based OTRAs model can be used in CAD tools. In this manner, the fully&#150;symbolic transfer functions of several application circuits, such as filters and oscillators can easily be approximated.</font></p>     ]]></body>
<body><![CDATA[<p align="justify"><font face="verdana" size="2"><b>Keywords:</b> Operational Transresistance Amplifier, nullor, nodal analysis.</font></p>     <p align="justify"><font face="verdana" size="2">&nbsp;</font></p>     <p align="justify"><font face="verdana" size="2"><b>RESUMEN</b></font></p>     <p align="justify"><font face="verdana" size="2">En el presente trabajo se presenta un nuevo modelo basado en nullors para describir el comportamiento de amplificadores operacionales de transresistencia (OTRAs). El modelo se compone de cuatro nullors y tres resistores aterrizados; como resultado, se puede aplicar el an&aacute;lisis nodal est&aacute;ndar para calcular caracter&iacute;sticas de peque&ntilde;a se&ntilde;al completamente simb&oacute;licas de circuitos anal&oacute;gicos basados en OTRAs; este nuevo modelo puede ser usado en herramientas CAD. De esta forma, las funciones de transferencia completamente simb&oacute;lica de varios circuitos de aplicaci&oacute;n tales como filtros y osciladores, pueden aproximarse f&aacute;cilmente.</font></p>     <p align="justify"><font face="verdana" size="2">&nbsp;</font></p>     <p align="justify"><font face="verdana" size="2"><a href="/pdf/jart/v9n1/v9n1a6.pdf" target="_blank">DESCARGAR ART&Iacute;CULO EN FORMATO PDF</a></font></p>     <p align="justify"><font face="verdana" size="2">&nbsp;</font></p>     <p align="justify"><font face="verdana" size="2"><b><i>Acknowledgment</i></b></font></p>     <p align="justify"><font face="verdana" size="2">This work has been supported by PROMEP&#150;Mexico under the project number UATLX&#150;PTC&#150;088 and by Consejer&iacute;a de Innovaci&oacute;n, Ciencia y Empresa, Junta de Andaluc&iacute;a&#150;Spain, under the project number TIC&#150;2532. The first author thanks the support from the JAE&#150;Doc program of CSIC, co&#150;funded by FSE.</font></p>     <p align="justify"><font face="verdana" size="2">&nbsp;</font></p>     ]]></body>
<body><![CDATA[<p align="justify"><font face="verdana" size="2"><b><i>References</i></b></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;1&#93;&nbsp;Brodie J.H. A Notch filter employing current differencing operational amplifier, <i>Int. J. Electron, </i>vol. 41, no. 5, pp. 501&#150;508, 1976.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825485&pid=S1665-6423201100010000600001&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;2&#93; Agouridis D.C, Fox R.J. Transresistance instrumentation amplifier, <i>Proc. IEEE, </i>vol. 66, no. 10, pp. 1286 &#150;1287, 1978.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825487&pid=S1665-6423201100010000600002&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;3&#93; National Semiconductors Corp., Designing with a new super fast dual norton amplifier. Linear Applications Data Book, 1981.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825489&pid=S1665-6423201100010000600003&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;4&#93; Abidi A. Gigahertz transresistance amplifiers in fine line NMOS, <i>IEEE </i>Journal Solid State Circuits, vol. 19, no. 6, pp. 986&#150;994, 1984.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825491&pid=S1665-6423201100010000600004&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;5&#93; National Semiconductors Corp., The LM 3900: a new current differencing &plusmn; quad of the input amplifiers. Linear Applications Data Book, 1986.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825493&pid=S1665-6423201100010000600005&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;6&#93; Chen J, Tsao H, Chen C. Operational transresistance amplifier using CMOS technology. <i>Electronics Letters, </i>vol. 28, no. 22, pp. 2087&#150;2088, 1992.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825495&pid=S1665-6423201100010000600006&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;7&#93; Salama K.N, Soliman A.M. CMOS operational transresistance amplifier for analog signal processing. <i>Microelectronics Journal, </i>vol. 30, no. 3, pp. 235&#150;245, 1999.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825497&pid=S1665-6423201100010000600007&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;8&#93; Salama K.N, Soliman A.M. Active RC applications of the operational transresistance amplifier. <i>Frequenz, </i>vol. 54, no. 1, pp. 171&#150;176, 2000.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825499&pid=S1665-6423201100010000600008&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;9&#93; Salama K.N, Soliman A.M. Novel oscillators using the operational transresistance amplifier. <i>Microelectronics Journal, </i>vol. 31, no. 1, pp. 39&#150;47, 2000.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825501&pid=S1665-6423201100010000600009&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;10&#93; Barthelemy H. Koudobine I, Landeghem D. Bipolar Low&#150;Power Operational Transresistance Amplifier Based on First Generation Current Conveyor, <i>IEEE Trans. </i>on <i>Circuits and systems II: Analog and Digital Signal Processing, </i>vol. 48, no. 6, pp. 620&#150;625, 2001.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825503&pid=S1665-6423201100010000600010&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;11&#93;&nbsp;Chen J.J, Tsao H.W, Liu S.I. Voltage&#150;mode MOSFET&#150;C filters using operational transresistance amplifier (OTRA's) with reduced parasitic capacitance effect. <i>IEE Proc. Circuits Devices Syst., </i>vol. 148, no. 5, pp. 242&#150;249, 2001.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825505&pid=S1665-6423201100010000600011&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;12&#93; Cam U, Kacar F, Cicekoglu O, Kuntman H, Kuntman A. Novel two OTRA&#150;based grounded immitance simulator topologies. <i>Analog Integrated Circuits and Signal Processing, </i>vol. 39, no. 2, pp. 169&#150;175, 2004.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825507&pid=S1665-6423201100010000600012&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;13&#93; Hou C.L, Chien H.C, Lo Y.K. Square wave generators employing OTRA's. <i>IEE Proc., Circuits Devices Syst., </i>vol. 152, no. 3, pp. 718&#150;722, 2005.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825509&pid=S1665-6423201100010000600013&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;14&#93; Cakir C, Cam U, Cicekoglu O. Novel all&#150;pass filter configuration employing single OTRA. <i>IEEE Transactions on Circuits and Systems II: Express Briefs, </i>vol. 52, no. 3, pp. 122&#150;125, 2005.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825511&pid=S1665-6423201100010000600014&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;15&#93; Kilinc S, Cam U. Realization of n&#150;th order voltage transfer function using a single operational transresistance amplifier. <i>ETRI Journal, </i>vol. 27, no. 5, pp. 647&#150;650, 2005.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825513&pid=S1665-6423201100010000600015&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;16&#93; Lo Y.K, Chien H.C. Current&#150;mode monostable multivibrators using OTRAs. <i>IEEE Transactions on Circuits and Systems II, </i>vol. 53, no. 11, pp. 1274&#150;1278, 2006.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825515&pid=S1665-6423201100010000600016&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;17&#93; Hwang Y.S, Wu D.S, Chen J.J, Shih C.C, Chou W.S. Realization of high&#150;order OTRA&#150;Mosfet&#150;C active filters. <i>Circuits Systems Signal Processing, </i>vol. 26, no. 4, pp. 281&#150;291, 2007.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825517&pid=S1665-6423201100010000600017&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;18&#93; Lo Y.K, Chien H.C. Switch&#150;controllable OTRA&#150;based square/triangular waveform generator. IEEE <i>Transactions on Circuits and Systems II, </i>vol. 54, no. 12, pp. 1110&#150;1114, 2007.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825519&pid=S1665-6423201100010000600018&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;19&#93; Lo Y.K, Chien H.C, Chiu H.J. Switch&#150;controllable OTRA&#150;based bistable multivibrators. <i>IET Circuits Devices Systems, </i>vol. 2, no. 4, pp. 373&#150;382, 2008.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825521&pid=S1665-6423201100010000600019&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;20&#93; Mitra, S. K. Nullator&#150;norator equivalent circuits of linear active elements and their applications. <i>Proceedings of Asilomar Conference on Circuits and Systems, </i>pp. 267&#150;276, Pacific Grove USA, November 1&#150;4, 1967.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825523&pid=S1665-6423201100010000600020&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;21&#93; Kumar P, Senani R. Bibliography on nullors and their applications in circuit analysis, synthesis and design. <i>Analog Integrated Circuits and Signal Processing, </i>vol. 33, no. 1, pp. 65&#150;76, 2002.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825525&pid=S1665-6423201100010000600021&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;22&#93; Svoboda JA. Current conveyors, operational amplifiers and nullors. <i>IEE Proceedings G Circuits, Devices &amp; Systems, </i>vol. 136, no. 6, pp. 317&#150;322, 1989</font>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825527&pid=S1665-6423201100010000600022&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --><!-- ref --><p align="justify"><font face="verdana" size="2">&#91;23&#93; Svoboda JA. Using nullors to analyse linear networks. <i>International Journal of Circuit Theory and Applications, </i>vol. 14, no. 3, pp. 169&#150;180, 1986.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825528&pid=S1665-6423201100010000600023&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;24&#93; Svoboda JA. Unique solvability of RLC nullor networks. <i>International Journal of Circuit Theory and Applications, </i>vol. 11, no. 1, pp. 1&#150;6, 1983.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825530&pid=S1665-6423201100010000600024&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;25&#93; Floberg H. <i>Symbolic Analysis in Analog Integrated Circuit Design. </i>Kluwer Academic Publishers, Boston, 1997.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825532&pid=S1665-6423201100010000600025&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     ]]></body>
<body><![CDATA[<!-- ref --><p align="justify"><font face="verdana" size="2">&#91;26&#93; Tlelo&#150;Cuautle E, S&aacute;nchez&#150;L&oacute;pez C, Sandoval&#150;Ibarra F. Computing symbolic expressions in analog circuits using nullors. <i>Computaci&oacute;n y Sistemas, </i>vol. 9, no. 2, pp. 119&#150;132, 2005.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825534&pid=S1665-6423201100010000600026&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;27&#93; Tlelo&#150;Cuautle E, S&aacute;nchez&#150;L&oacute;pez C, Moro&#150;Fr&iacute;as D. Symbolic analysis of (MO)(I)CCI(II)(III)&#150;based analog circuits. <i>International Journal of Circuit. Theory and Applications, </i>vol. 38, no. 6 pp. 649&#150;650, 2010.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825536&pid=S1665-6423201100010000600027&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;28&#93; Schmid H. Approximating the universal active element. <i>IEEE Trans on Circuits and Systems II: Analog and Digital Signal Processing, </i>vol. 47, no. 11, pp. 11601169, 2000.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825538&pid=S1665-6423201100010000600028&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;29&#93; S&aacute;nchez&#150;L&oacute;pez C, Tlelo&#150;Cuautle E. Behavioral model generation for symbolic analysis of analog integrated circuits. <i>IEEE ISSCS, </i>pp. 327&#150;330, Iasi, Romania, July 14&#150;15, 2005.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825540&pid=S1665-6423201100010000600029&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;30&#93; S&aacute;nchez&#150;L&oacute;pez C, Tlelo&#150;Cuautle E. Symbolic behavioral model generation of current&#150;mode analog circuits. <i>IEEE ISCAS, </i>pp. 2761&#150;2764, Taipei, Taiwan, May 24&#150;27, 2009.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825542&pid=S1665-6423201100010000600030&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     ]]></body>
<body><![CDATA[<!-- ref --><p align="justify"><font face="verdana" size="2">&#91;31&#93; S&aacute;nchez&#150;L&oacute;pez C, Moro&#150;Fr&iacute;as D, Tlelo&#150;Cuautle E. Improving the formulation process of the system of equations of analog circuits, <i>IEEE SM2ACD, </i>pp. 102106, Erfurt, Germany, October 7&#150;8, 2008.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825544&pid=S1665-6423201100010000600031&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;32&#93; Tlelo&#150;Cuautle E, S&aacute;nchez&#150;L&oacute;pez C, Martinez&#150;Romero E, S.X.&#150;D. Tan  Symbolic analysis of analog circuits containing voltage mirrors and current mirrors, <i>Analog Integrated Circuits and Signal Processing, </i>vol. 65, no. 1, pp 89&#150;95, 2010.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825546&pid=S1665-6423201100010000600032&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;33&#93; Tan S. X.&#150;D. Symbolic analysis of analog circuits by Boolean logic operators. <i>IEEE Trans on Circuits and Systems II: Express Briefs, </i>vol. 53, no. 11, pp. 13131317, 2006.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825548&pid=S1665-6423201100010000600033&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;34&#93; Tan S. X.&#150;D, Guo W, Qi Z. Hierarchical approach to exact symbolic analysis of large analog circuits. IEEE Trans on <i>Computer&#150;Aided Design of Integrated Circuits and Systems, </i>vol. 24, no. 8, pp. 1241&#150;1250, 2005.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825550&pid=S1665-6423201100010000600034&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;35&#93; Doboli A, Vemuri R. A regularity&#150;based hierarchical symbolic analysis method for large&#150;scale analog networks. <i>IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, </i>vol. 48, no. 11, pp. 1054&#150;1068, 2001.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825552&pid=S1665-6423201100010000600035&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     ]]></body>
<body><![CDATA[<!-- ref --><p align="justify"><font face="verdana" size="2">&#91;36&#93; Gielen G, Wambacq P, Sansen W. Symbolic analysis methods and applications for analog circuits: a tutorial overview. <i>Proceedings of the IEEE, </i>vol. 82, no. 2, pp. 287&#150;304, 1994.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825554&pid=S1665-6423201100010000600036&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;37&#93; Wambacq P, Fern&aacute;ndez F.V. Gielen G, Sansen W, Rodr&iacute;guez&#150;V&aacute;zquez A. Algorithm for efficient symbolic analysis of large analogue circuits. <i>Electronics Letters, </i>vol. 30, no. 14, pp. 1108&#150;1109, 1994.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825556&pid=S1665-6423201100010000600037&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;38&#93; Chua LO, Lin PM. <i>Computer&#150;Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques. </i>Prentice&#150;Hall: Englewood Cliffs, NJ, 1975.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825558&pid=S1665-6423201100010000600038&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;39&#93; Gielen GE, Sansen W. Symbolic <i>Analysis for Automated Design of Analog Integrated Circuits. </i>Kluwer Academic Publishers, 1991.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825560&pid=S1665-6423201100010000600039&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;40&#93; Fern&aacute;ndez F.V., Rodr&iacute;guez&#150;V&aacute;zquez A, Huertas JL, Gielen GE. <i>Symbolic Analysis Techniques: Applications to Analog Design Automation. </i>IEEE Press: NY, 1998.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825562&pid=S1665-6423201100010000600040&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     ]]></body>
<body><![CDATA[<!-- ref --><p align="justify"><font face="verdana" size="2">&#91;41&#93; Shi CJR, Tan XD. Canonical symbolic analysis of large analog circuits with determinant decision diagrams. <i>IEEE Transactions on Computer&#150;Aided Design of Integrated Circuits and Systems, </i>vol. 19, no. 1, pp. 1&#150;18, 2000.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825564&pid=S1665-6423201100010000600041&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;42&#93; S&aacute;nchez&#150;L&oacute;pez C, Fern&aacute;ndez F.V, Tlelo&#150;Cuautle E. Generalized Admittance Matrix Models of OTRAs and COAs. <i>Microelectronics Journal, </i>vol. 41, no. 8, pp. 502505, 2010.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825566&pid=S1665-6423201100010000600042&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;43&#93; Haigh D.G, Clarke T.J.W, Radmore P.M. Symbolic framework for linear active circuits based on port equivalence using limit variables. <i>IEEE Trans. Circuits Syst. I: Reg. Papers, </i>vol. 53, no. 9, pp. 2011&#150;2024, 2006.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825568&pid=S1665-6423201100010000600043&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;44&#93; Haigh D.G. A method of transformation from symbolic transfer function to active&#150;RC circuit by admittance matrix expansion. <i>IEEE Trans. Circuits Syst. I: Reg. Papers, </i>vol. 53, no. 12, pp. 2715&#150;2728, 2006.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825570&pid=S1665-6423201100010000600044&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;45&#93; Haigh D.G, Radmore P.M. Admittance matrix models for the nullor using limit variables and their application to circuit design. <i>IEEE Trans. Circuits Syst. I: Reg. Papers, </i>vol. 53, no. 10, pp. 2214&#150;2223, 2006.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825572&pid=S1665-6423201100010000600045&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     ]]></body>
<body><![CDATA[<!-- ref --><p align="justify"><font face="verdana" size="2">&#91;46&#93; Haigh D.G, Tan F.Q, Papavassiliou C. Systematic synthesis of active&#150;RC circuit building&#150;blocks. <i>Anal. Integr. Circuits Signal Processing, </i>vol. 43, no. 3, pp. 297315, 2005.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825574&pid=S1665-6423201100010000600046&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;47&#93; Awad I.A., Soliman A.M. On the voltage mirrors and the current mirrors. <i>Anal. Integr. Circuits Signal Processing, </i>vol. 32, no. 1, pp. 79&#150;81, 2002.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825576&pid=S1665-6423201100010000600047&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;48&#93; Soliman A.M, Saad R.A. The voltage mirror&#150;current mirror pair as a universal element. <i>International Journal of Circuit Theory and Applications </i>2009; DOI: 10.1002/cta.596</font>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825578&pid=S1665-6423201100010000600048&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --><!-- ref --><p align="justify"><font face="verdana" size="2">&#91;49&#93; S&aacute;nchez&#150;L&oacute;pez C, Fern&aacute;ndez F.V, Tlelo&#150;Cuatle E, S.X.&#150;D. Tan  Pathological element&#150;based active device models and their application to symbolic analysis, <i>IEEE Transactions on Circuits and Systems I: Regular papers, </i>2011. DOI: 10.1109/TCSI.2010.20097696.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4825579&pid=S1665-6423201100010000600049&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>      ]]></body><back>
<ref-list>
<ref id="B1">
<label>1</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Brodie]]></surname>
<given-names><![CDATA[J.H.]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[A Notch filter employing current differencing operational amplifier]]></article-title>
<source><![CDATA[Int. J. Electron]]></source>
<year>1976</year>
<volume>41</volume>
<numero>5</numero>
<issue>5</issue>
<page-range>501-508</page-range></nlm-citation>
</ref>
<ref id="B2">
<label>2</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Agouridis]]></surname>
<given-names><![CDATA[D.C]]></given-names>
</name>
<name>
<surname><![CDATA[Fox]]></surname>
<given-names><![CDATA[R.J.]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Transresistance instrumentation amplifier]]></article-title>
<source><![CDATA[Proc. IEEE]]></source>
<year>1978</year>
<volume>66</volume>
<numero>10</numero>
<issue>10</issue>
<page-range>1286 -1287</page-range></nlm-citation>
</ref>
<ref id="B3">
<label>3</label><nlm-citation citation-type="">
<collab>National Semiconductors</collab>
<source><![CDATA[Designing with a new super fast dual norton amplifier]]></source>
<year>1981</year>
</nlm-citation>
</ref>
<ref id="B4">
<label>4</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Abidi]]></surname>
<given-names><![CDATA[A]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Gigahertz transresistance amplifiers in fine line NMOS]]></article-title>
<source><![CDATA[IEEE Journal Solid State Circuits]]></source>
<year>1984</year>
<volume>19</volume>
<numero>6</numero>
<issue>6</issue>
<page-range>986-994</page-range></nlm-citation>
</ref>
<ref id="B5">
<label>5</label><nlm-citation citation-type="">
<collab>National Semiconductors</collab>
<source><![CDATA[The LM 3900: a new current differencing ± quad of the input amplifiers]]></source>
<year>1986</year>
</nlm-citation>
</ref>
<ref id="B6">
<label>6</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Chen]]></surname>
<given-names><![CDATA[J]]></given-names>
</name>
<name>
<surname><![CDATA[Tsao]]></surname>
<given-names><![CDATA[H]]></given-names>
</name>
<name>
<surname><![CDATA[Chen]]></surname>
<given-names><![CDATA[C]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Operational transresistance amplifier using CMOS technology]]></article-title>
<source><![CDATA[Electronics Letters]]></source>
<year>1992</year>
<volume>28</volume>
<numero>22</numero>
<issue>22</issue>
<page-range>2087-2088</page-range></nlm-citation>
</ref>
<ref id="B7">
<label>7</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Salama]]></surname>
<given-names><![CDATA[K.N]]></given-names>
</name>
<name>
<surname><![CDATA[Soliman]]></surname>
<given-names><![CDATA[A.M.]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[CMOS operational transresistance amplifier for analog signal processing]]></article-title>
<source><![CDATA[Microelectronics Journal]]></source>
<year>1999</year>
<volume>30</volume>
<numero>3</numero>
<issue>3</issue>
<page-range>235-245</page-range></nlm-citation>
</ref>
<ref id="B8">
<label>8</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Salama]]></surname>
<given-names><![CDATA[K.N]]></given-names>
</name>
<name>
<surname><![CDATA[Soliman]]></surname>
<given-names><![CDATA[A.M.]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Active RC applications of the operational transresistance amplifier]]></article-title>
<source><![CDATA[Frequenz]]></source>
<year>2000</year>
<volume>54</volume>
<numero>1</numero>
<issue>1</issue>
<page-range>171-176</page-range></nlm-citation>
</ref>
<ref id="B9">
<label>9</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Salama]]></surname>
<given-names><![CDATA[K.N]]></given-names>
</name>
<name>
<surname><![CDATA[Soliman]]></surname>
<given-names><![CDATA[A.M.]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Novel oscillators using the operational transresistance amplifier]]></article-title>
<source><![CDATA[Microelectronics Journal]]></source>
<year>2000</year>
<volume>31</volume>
<numero>1</numero>
<issue>1</issue>
<page-range>39-47</page-range></nlm-citation>
</ref>
<ref id="B10">
<label>10</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Barthelemy]]></surname>
<given-names><![CDATA[H]]></given-names>
</name>
<name>
<surname><![CDATA[Koudobine]]></surname>
<given-names><![CDATA[I]]></given-names>
</name>
<name>
<surname><![CDATA[Landeghem]]></surname>
<given-names><![CDATA[D]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Bipolar Low-Power Operational Transresistance Amplifier Based on First Generation Current Conveyor]]></article-title>
<source><![CDATA[IEEE Trans. on Circuits and systems II: Analog and Digital Signal Processing]]></source>
<year>2001</year>
<volume>48</volume>
<numero>6</numero>
<issue>6</issue>
<page-range>620-625</page-range></nlm-citation>
</ref>
<ref id="B11">
<label>11</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Chen]]></surname>
<given-names><![CDATA[J.J]]></given-names>
</name>
<name>
<surname><![CDATA[Tsao]]></surname>
<given-names><![CDATA[H.W]]></given-names>
</name>
<name>
<surname><![CDATA[Liu]]></surname>
<given-names><![CDATA[S.I.]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Voltage-mode MOSFET-C filters using operational transresistance amplifier (OTRA's) with reduced parasitic capacitance effect]]></article-title>
<source><![CDATA[IEE Proc. Circuits Devices Syst.]]></source>
<year>2001</year>
<volume>148</volume>
<numero>5</numero>
<issue>5</issue>
<page-range>242-249</page-range></nlm-citation>
</ref>
<ref id="B12">
<label>12</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Cam]]></surname>
<given-names><![CDATA[U]]></given-names>
</name>
<name>
<surname><![CDATA[Kacar]]></surname>
<given-names><![CDATA[F]]></given-names>
</name>
<name>
<surname><![CDATA[Cicekoglu]]></surname>
<given-names><![CDATA[O]]></given-names>
</name>
<name>
<surname><![CDATA[Kuntman]]></surname>
<given-names><![CDATA[H]]></given-names>
</name>
<name>
<surname><![CDATA[Kuntman]]></surname>
<given-names><![CDATA[A]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Novel two OTRA-based grounded immitance simulator topologies]]></article-title>
<source><![CDATA[Analog Integrated Circuits and Signal Processing]]></source>
<year>2004</year>
<volume>39</volume>
<numero>2</numero>
<issue>2</issue>
<page-range>169-175</page-range></nlm-citation>
</ref>
<ref id="B13">
<label>13</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Hou]]></surname>
<given-names><![CDATA[C.L]]></given-names>
</name>
<name>
<surname><![CDATA[Chien]]></surname>
<given-names><![CDATA[H.C]]></given-names>
</name>
<name>
<surname><![CDATA[Lo]]></surname>
<given-names><![CDATA[Y.K.]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Square wave generators employing OTRA's]]></article-title>
<source><![CDATA[IEE Proc., Circuits Devices Syst.]]></source>
<year>2005</year>
<volume>152</volume>
<numero>3</numero>
<issue>3</issue>
<page-range>718-722</page-range></nlm-citation>
</ref>
<ref id="B14">
<label>14</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Cakir]]></surname>
<given-names><![CDATA[C]]></given-names>
</name>
<name>
<surname><![CDATA[Cam]]></surname>
<given-names><![CDATA[U]]></given-names>
</name>
<name>
<surname><![CDATA[Cicekoglu]]></surname>
<given-names><![CDATA[O]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Novel all-pass filter configuration employing single OTRA]]></article-title>
<source><![CDATA[IEEE Transactions on Circuits and Systems II: Express Briefs]]></source>
<year>2005</year>
<volume>52</volume>
<numero>3</numero>
<issue>3</issue>
<page-range>122-125</page-range></nlm-citation>
</ref>
<ref id="B15">
<label>15</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Kilinc]]></surname>
<given-names><![CDATA[S]]></given-names>
</name>
<name>
<surname><![CDATA[Cam]]></surname>
<given-names><![CDATA[U]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Realization of n-th order voltage transfer function using a single operational transresistance amplifier]]></article-title>
<source><![CDATA[ETRI Journal]]></source>
<year>2005</year>
<volume>27</volume>
<numero>5</numero>
<issue>5</issue>
<page-range>647-650</page-range></nlm-citation>
</ref>
<ref id="B16">
<label>16</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Lo]]></surname>
<given-names><![CDATA[Y.K]]></given-names>
</name>
<name>
<surname><![CDATA[Chien]]></surname>
<given-names><![CDATA[H.C.]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Current-mode monostable multivibrators using OTRAs]]></article-title>
<source><![CDATA[IEEE Transactions on Circuits and Systems II]]></source>
<year>2006</year>
<volume>53</volume>
<numero>11</numero>
<issue>11</issue>
<page-range>1274-1278</page-range></nlm-citation>
</ref>
<ref id="B17">
<label>17</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Hwang]]></surname>
<given-names><![CDATA[Y.S]]></given-names>
</name>
<name>
<surname><![CDATA[Wu]]></surname>
<given-names><![CDATA[D.S]]></given-names>
</name>
<name>
<surname><![CDATA[Chen]]></surname>
<given-names><![CDATA[J.J]]></given-names>
</name>
<name>
<surname><![CDATA[Shih]]></surname>
<given-names><![CDATA[C.C]]></given-names>
</name>
<name>
<surname><![CDATA[Chou]]></surname>
<given-names><![CDATA[W.S.]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Realization of high-order OTRA-Mosfet-C active filters]]></article-title>
<source><![CDATA[Circuits Systems Signal Processing]]></source>
<year>2007</year>
<volume>26</volume>
<numero>4</numero>
<issue>4</issue>
<page-range>281-291</page-range></nlm-citation>
</ref>
<ref id="B18">
<label>18</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Lo]]></surname>
<given-names><![CDATA[Y.K]]></given-names>
</name>
<name>
<surname><![CDATA[Chien]]></surname>
<given-names><![CDATA[H.C.]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Switch-controllable OTRA-based square/triangular waveform generator]]></article-title>
<source><![CDATA[IEEE Transactions on Circuits and Systems II]]></source>
<year>2007</year>
<volume>54</volume>
<numero>12</numero>
<issue>12</issue>
<page-range>1110-1114</page-range></nlm-citation>
</ref>
<ref id="B19">
<label>19</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Lo]]></surname>
<given-names><![CDATA[Y.K]]></given-names>
</name>
<name>
<surname><![CDATA[Chien]]></surname>
<given-names><![CDATA[H.C]]></given-names>
</name>
<name>
<surname><![CDATA[Chiu]]></surname>
<given-names><![CDATA[H.J.]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Switch-controllable OTRA-based bistable multivibrators]]></article-title>
<source><![CDATA[IET Circuits Devices Systems]]></source>
<year>2008</year>
<volume>2</volume>
<numero>4</numero>
<issue>4</issue>
<page-range>. 373-382</page-range></nlm-citation>
</ref>
<ref id="B20">
<label>20</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Mitra]]></surname>
<given-names><![CDATA[S. K.]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Nullator-norator equivalent circuits of linear active elements and their applications]]></article-title>
<source><![CDATA[Proceedings of Asilomar Conference on Circuits and Systems]]></source>
<year>1967</year>
<page-range>267-276</page-range><publisher-name><![CDATA[Pacific Grove USA]]></publisher-name>
</nlm-citation>
</ref>
<ref id="B21">
<label>21</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Kumar]]></surname>
<given-names><![CDATA[P]]></given-names>
</name>
<name>
<surname><![CDATA[Senani]]></surname>
<given-names><![CDATA[R]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Bibliography on nullors and their applications in circuit analysis, synthesis and design]]></article-title>
<source><![CDATA[Analog Integrated Circuits and Signal Processing]]></source>
<year>2002</year>
<volume>33</volume>
<numero>1</numero>
<issue>1</issue>
<page-range>65-76</page-range></nlm-citation>
</ref>
<ref id="B22">
<label>22</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Svoboda]]></surname>
<given-names><![CDATA[JA]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Current conveyors, operational amplifiers and nullors]]></article-title>
<source><![CDATA[IEE Proceedings G Circuits, Devices & Systems]]></source>
<year>1989</year>
<volume>136</volume>
<numero>6</numero>
<issue>6</issue>
<page-range>317-322</page-range></nlm-citation>
</ref>
<ref id="B23">
<label>23</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Svoboda]]></surname>
<given-names><![CDATA[JA]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Using nullors to analyse linear networks]]></article-title>
<source><![CDATA[International Journal of Circuit Theory and Applications]]></source>
<year>1986</year>
<volume>14</volume>
<numero>3</numero>
<issue>3</issue>
<page-range>169-180</page-range></nlm-citation>
</ref>
<ref id="B24">
<label>24</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Svoboda]]></surname>
<given-names><![CDATA[JA]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Unique solvability of RLC nullor networks]]></article-title>
<source><![CDATA[International Journal of Circuit Theory and Applications]]></source>
<year>1983</year>
<volume>11</volume>
<numero>1</numero>
<issue>1</issue>
<page-range>1-6</page-range></nlm-citation>
</ref>
<ref id="B25">
<label>25</label><nlm-citation citation-type="book">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Floberg]]></surname>
<given-names><![CDATA[H]]></given-names>
</name>
</person-group>
<source><![CDATA[Symbolic Analysis in Analog Integrated Circuit Design]]></source>
<year>1997</year>
<publisher-loc><![CDATA[^eBoston Boston]]></publisher-loc>
<publisher-name><![CDATA[Kluwer Academic Publishers]]></publisher-name>
</nlm-citation>
</ref>
<ref id="B26">
<label>26</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Tlelo-Cuautle]]></surname>
<given-names><![CDATA[E]]></given-names>
</name>
<name>
<surname><![CDATA[Sánchez-López]]></surname>
<given-names><![CDATA[C]]></given-names>
</name>
<name>
<surname><![CDATA[Sandoval-Ibarra]]></surname>
<given-names><![CDATA[F]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Computing symbolic expressions in analog circuits using nullors]]></article-title>
<source><![CDATA[Computación y Sistemas]]></source>
<year>2005</year>
<volume>9</volume>
<numero>2</numero>
<issue>2</issue>
<page-range>119-132</page-range></nlm-citation>
</ref>
<ref id="B27">
<label>27</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Tlelo-Cuautle]]></surname>
<given-names><![CDATA[E]]></given-names>
</name>
<name>
<surname><![CDATA[Sánchez-López]]></surname>
<given-names><![CDATA[C]]></given-names>
</name>
<name>
<surname><![CDATA[Moro-Frías]]></surname>
<given-names><![CDATA[D]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Symbolic analysis of (MO)(I)CCI(II)(III)-based analog circuits]]></article-title>
<source><![CDATA[International Journal of Circuit. Theory and Applications]]></source>
<year>2010</year>
<volume>38</volume>
<numero>6</numero>
<issue>6</issue>
<page-range>649-650</page-range></nlm-citation>
</ref>
<ref id="B28">
<label>28</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Schmid]]></surname>
<given-names><![CDATA[H]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Approximating the universal active element]]></article-title>
<source><![CDATA[IEEE Trans on Circuits and Systems II: Analog and Digital Signal Processing]]></source>
<year>2000</year>
<volume>47</volume>
<numero>11</numero>
<issue>11</issue>
<page-range>11601169</page-range></nlm-citation>
</ref>
<ref id="B29">
<label>29</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Sánchez-López]]></surname>
<given-names><![CDATA[C]]></given-names>
</name>
<name>
<surname><![CDATA[Tlelo-Cuautle]]></surname>
<given-names><![CDATA[E]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Behavioral model generation for symbolic analysis of analog integrated circuits]]></article-title>
<source><![CDATA[IEEE ISSCS]]></source>
<year>2005</year>
<page-range>327-330</page-range><publisher-loc><![CDATA[Iasi ]]></publisher-loc>
</nlm-citation>
</ref>
<ref id="B30">
<label>30</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Sánchez-López]]></surname>
<given-names><![CDATA[C]]></given-names>
</name>
<name>
<surname><![CDATA[Tlelo-Cuautle]]></surname>
<given-names><![CDATA[E]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Symbolic behavioral model generation of current-mode analog circuits]]></article-title>
<source><![CDATA[IEEE ISCAS]]></source>
<year>2009</year>
<page-range>2761-2764</page-range><publisher-loc><![CDATA[TaipeiTaiwan ]]></publisher-loc>
</nlm-citation>
</ref>
<ref id="B31">
<label>31</label><nlm-citation citation-type="">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Sánchez-López]]></surname>
<given-names><![CDATA[C]]></given-names>
</name>
<name>
<surname><![CDATA[Moro-Frías]]></surname>
<given-names><![CDATA[D]]></given-names>
</name>
<name>
<surname><![CDATA[Tlelo-Cuautle]]></surname>
<given-names><![CDATA[E]]></given-names>
</name>
</person-group>
<source><![CDATA[Improving the formulation process of the system of equations of analog circuits, IEEE SM2ACD]]></source>
<year>2008</year>
<page-range>102106</page-range><publisher-loc><![CDATA[Erfurt ]]></publisher-loc>
</nlm-citation>
</ref>
<ref id="B32">
<label>32</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Tlelo-Cuautle]]></surname>
<given-names><![CDATA[E]]></given-names>
</name>
<name>
<surname><![CDATA[Sánchez-López]]></surname>
<given-names><![CDATA[C]]></given-names>
</name>
<name>
<surname><![CDATA[Martinez-Romero]]></surname>
<given-names><![CDATA[E]]></given-names>
</name>
<name>
<surname><![CDATA[Tan]]></surname>
<given-names><![CDATA[S.X.-D.]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Symbolic analysis of analog circuits containing voltage mirrors and current mirrors]]></article-title>
<source><![CDATA[Analog Integrated Circuits and Signal Processing]]></source>
<year>2010</year>
<volume>65</volume>
<numero>1</numero>
<issue>1</issue>
<page-range>89-95</page-range></nlm-citation>
</ref>
<ref id="B33">
<label>33</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Tan]]></surname>
<given-names><![CDATA[S. X.-D.]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Symbolic analysis of analog circuits by Boolean logic operators]]></article-title>
<source><![CDATA[IEEE Trans on Circuits and Systems II: Express Briefs]]></source>
<year>2006</year>
<volume>53</volume>
<numero>11</numero>
<issue>11</issue>
<page-range>13131317</page-range></nlm-citation>
</ref>
<ref id="B34">
<label>34</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Tan]]></surname>
<given-names><![CDATA[S. X.-D]]></given-names>
</name>
<name>
<surname><![CDATA[Guo]]></surname>
<given-names><![CDATA[W]]></given-names>
</name>
<name>
<surname><![CDATA[Qi]]></surname>
<given-names><![CDATA[Z]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Hierarchical approach to exact symbolic analysis of large analog circuits]]></article-title>
<source><![CDATA[IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems]]></source>
<year>2005</year>
<volume>24</volume>
<numero>8</numero>
<issue>8</issue>
<page-range>1241-1250</page-range></nlm-citation>
</ref>
<ref id="B35">
<label>35</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Doboli]]></surname>
<given-names><![CDATA[A]]></given-names>
</name>
<name>
<surname><![CDATA[Vemuri]]></surname>
<given-names><![CDATA[R]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[A regularity-based hierarchical symbolic analysis method for large-scale analog networks]]></article-title>
<source><![CDATA[IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing]]></source>
<year>2001</year>
<volume>48</volume>
<numero>11</numero>
<issue>11</issue>
<page-range>1054-1068</page-range></nlm-citation>
</ref>
<ref id="B36">
<label>36</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Gielen]]></surname>
<given-names><![CDATA[G]]></given-names>
</name>
<name>
<surname><![CDATA[Wambacq]]></surname>
<given-names><![CDATA[P]]></given-names>
</name>
<name>
<surname><![CDATA[Sansen]]></surname>
<given-names><![CDATA[W]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Symbolic analysis methods and applications for analog circuits: a tutorial overview]]></article-title>
<source><![CDATA[Proceedings of the IEEE]]></source>
<year>1994</year>
<volume>82</volume>
<numero>2</numero>
<issue>2</issue>
<page-range>287-304</page-range></nlm-citation>
</ref>
<ref id="B37">
<label>37</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Wambacq]]></surname>
<given-names><![CDATA[P]]></given-names>
</name>
<name>
<surname><![CDATA[Fernández]]></surname>
<given-names><![CDATA[F.V.]]></given-names>
</name>
<name>
<surname><![CDATA[Gielen]]></surname>
<given-names><![CDATA[G]]></given-names>
</name>
<name>
<surname><![CDATA[Sansen]]></surname>
<given-names><![CDATA[W]]></given-names>
</name>
<name>
<surname><![CDATA[Rodríguez-Vázquez]]></surname>
<given-names><![CDATA[A]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Algorithm for efficient symbolic analysis of large analogue circuits]]></article-title>
<source><![CDATA[Electronics Letters]]></source>
<year>1994</year>
<volume>30</volume>
<numero>14</numero>
<issue>14</issue>
<page-range>1108-1109</page-range></nlm-citation>
</ref>
<ref id="B38">
<label>38</label><nlm-citation citation-type="book">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Chua]]></surname>
<given-names><![CDATA[LO]]></given-names>
</name>
<name>
<surname><![CDATA[Lin]]></surname>
<given-names><![CDATA[PM]]></given-names>
</name>
</person-group>
<source><![CDATA[Computer-Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques]]></source>
<year>1975</year>
<publisher-loc><![CDATA[Englewood Cliffs^eNJ NJ]]></publisher-loc>
<publisher-name><![CDATA[Prentice-Hall]]></publisher-name>
</nlm-citation>
</ref>
<ref id="B39">
<label>39</label><nlm-citation citation-type="book">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Gielen]]></surname>
<given-names><![CDATA[GE]]></given-names>
</name>
<name>
<surname><![CDATA[Sansen]]></surname>
<given-names><![CDATA[W]]></given-names>
</name>
</person-group>
<source><![CDATA[Symbolic Analysis for Automated Design of Analog Integrated Circuits]]></source>
<year>1991</year>
<publisher-name><![CDATA[Kluwer Academic]]></publisher-name>
</nlm-citation>
</ref>
<ref id="B40">
<label>40</label><nlm-citation citation-type="book">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Fernández]]></surname>
<given-names><![CDATA[F.V.]]></given-names>
</name>
<name>
<surname><![CDATA[Rodríguez-Vázquez]]></surname>
<given-names><![CDATA[A]]></given-names>
</name>
<name>
<surname><![CDATA[Huertas]]></surname>
<given-names><![CDATA[JL]]></given-names>
</name>
<name>
<surname><![CDATA[Gielen]]></surname>
<given-names><![CDATA[GE]]></given-names>
</name>
</person-group>
<source><![CDATA[Symbolic Analysis Techniques: Applications to Analog Design Automation]]></source>
<year>1998</year>
<publisher-loc><![CDATA[NY ]]></publisher-loc>
<publisher-name><![CDATA[IEEE Press]]></publisher-name>
</nlm-citation>
</ref>
<ref id="B41">
<label>41</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Shi]]></surname>
<given-names><![CDATA[CJR]]></given-names>
</name>
<name>
<surname><![CDATA[Tan]]></surname>
<given-names><![CDATA[XD]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Canonical symbolic analysis of large analog circuits with determinant decision diagrams]]></article-title>
<source><![CDATA[IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems]]></source>
<year>2000</year>
<volume>19</volume>
<numero>1</numero>
<issue>1</issue>
<page-range>1-18</page-range></nlm-citation>
</ref>
<ref id="B42">
<label>42</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Sánchez-López]]></surname>
<given-names><![CDATA[C]]></given-names>
</name>
<name>
<surname><![CDATA[Fernández]]></surname>
<given-names><![CDATA[F.V]]></given-names>
</name>
<name>
<surname><![CDATA[Tlelo-Cuautle]]></surname>
<given-names><![CDATA[E]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Generalized Admittance Matrix Models of OTRAs and COAs]]></article-title>
<source><![CDATA[Microelectronics Journal]]></source>
<year>2010</year>
<volume>41</volume>
<numero>8</numero>
<issue>8</issue>
<page-range>502505</page-range></nlm-citation>
</ref>
<ref id="B43">
<label>43</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Haigh]]></surname>
<given-names><![CDATA[D.G]]></given-names>
</name>
<name>
<surname><![CDATA[Clarke]]></surname>
<given-names><![CDATA[T.J.W]]></given-names>
</name>
<name>
<surname><![CDATA[Radmore]]></surname>
<given-names><![CDATA[P.M.]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Symbolic framework for linear active circuits based on port equivalence using limit variables]]></article-title>
<source><![CDATA[IEEE Trans. Circuits Syst. I: Reg. Papers]]></source>
<year>2006</year>
<volume>53</volume>
<numero>9</numero>
<issue>9</issue>
<page-range>2011-2024</page-range></nlm-citation>
</ref>
<ref id="B44">
<label>44</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Haigh]]></surname>
<given-names><![CDATA[D.G.]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[A method of transformation from symbolic transfer function to active-RC circuit by admittance matrix expansion]]></article-title>
<source><![CDATA[IEEE Trans. Circuits Syst. I: Reg. Papers]]></source>
<year>2006</year>
<volume>53</volume>
<numero>12</numero>
<issue>12</issue>
<page-range>2715-2728</page-range></nlm-citation>
</ref>
<ref id="B45">
<label>45</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Haigh]]></surname>
<given-names><![CDATA[D.G]]></given-names>
</name>
<name>
<surname><![CDATA[Radmore]]></surname>
<given-names><![CDATA[P.M.]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Admittance matrix models for the nullor using limit variables and their application to circuit design]]></article-title>
<source><![CDATA[IEEE Trans. Circuits Syst. I: Reg. Papers]]></source>
<year>2006</year>
<volume>53</volume>
<numero>10</numero>
<issue>10</issue>
<page-range>2214-2223</page-range></nlm-citation>
</ref>
<ref id="B46">
<label>46</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Haigh]]></surname>
<given-names><![CDATA[D.G]]></given-names>
</name>
<name>
<surname><![CDATA[Tan]]></surname>
<given-names><![CDATA[F.Q]]></given-names>
</name>
<name>
<surname><![CDATA[Papavassiliou]]></surname>
<given-names><![CDATA[C]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Systematic synthesis of active-RC circuit building-blocks]]></article-title>
<source><![CDATA[Anal. Integr. Circuits Signal Processing]]></source>
<year>2005</year>
<volume>43</volume>
<numero>3</numero>
<issue>3</issue>
<page-range>297315</page-range></nlm-citation>
</ref>
<ref id="B47">
<label>47</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Awad]]></surname>
<given-names><![CDATA[I.A.]]></given-names>
</name>
<name>
<surname><![CDATA[Soliman]]></surname>
<given-names><![CDATA[A.M.]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[On the voltage mirrors and the current mirrors]]></article-title>
<source><![CDATA[Anal. Integr. Circuits Signal Processing]]></source>
<year>2002</year>
<volume>32</volume>
<numero>1</numero>
<issue>1</issue>
<page-range>79-81</page-range></nlm-citation>
</ref>
<ref id="B48">
<label>48</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Soliman]]></surname>
<given-names><![CDATA[A.M]]></given-names>
</name>
<name>
<surname><![CDATA[Saad]]></surname>
<given-names><![CDATA[R.A.]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[The voltage mirror-current mirror pair as a universal element]]></article-title>
<source><![CDATA[International Journal of Circuit Theory and Applications]]></source>
<year>2009</year>
</nlm-citation>
</ref>
<ref id="B49">
<label>49</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Sánchez-López]]></surname>
<given-names><![CDATA[C]]></given-names>
</name>
<name>
<surname><![CDATA[Fernández]]></surname>
<given-names><![CDATA[F.V]]></given-names>
</name>
<name>
<surname><![CDATA[Tlelo-Cuatle]]></surname>
<given-names><![CDATA[E]]></given-names>
</name>
<name>
<surname><![CDATA[Tan]]></surname>
<given-names><![CDATA[S.X.-D.]]></given-names>
</name>
</person-group>
<article-title xml:lang="en"><![CDATA[Pathological element-based active device models and their application to symbolic analysis]]></article-title>
<source><![CDATA[IEEE Transactions on Circuits and Systems I: Regular papers]]></source>
<year>2011</year>
</nlm-citation>
</ref>
</ref-list>
</back>
</article>
