D. Torres*¹, J. Cortéz², R. E. González¹

¹ Research Center and Advanced Studies of IPN, Av. Científica 1145, C.P. 44019, Zapopan, Jalisco, México. *E–mail:dtorres@gdl.cinvestav.mx

² ITSON, Antonio Caso S/N, C.P. 85130, Cd. Obregón, Sonora, México.

ABSTRACT

In this work, an improvement of the traditional digital design methodology is proposed. The major change is the use of a semi–formal specification for the code implementation, the use of a verification tool and the establishment of properties for the formal verification of Finite State Machines (FSM). From semi–formal specifications, assertions were written using Property Specification Language (PSL) for an alignment circuit. Finally, a set of properties for the verification of this module were established and proved using a model checking tool. Our statistics proved that the whole design process was improved and considerable design time was saved.

RESUMEN

En el presente trabajo se propone una mejora a la metodología del ciclo de diseño digital tradicional. La contribución principal es la generación de un conjunto de propiedades a partir de una especificación semi–formal de requerimientos, que permiten la verificación formal automática de una máquina de estados finitos (FSM). Estas propiedades se escriben en el lenguaje PSL. Se muestra cómo, a partir de las propiedades, se puede obtener código VHDL que implementa la máquina de estados. Nuestros resultados muestran que la metodología de diseño propuesta resulta en una disminución del tiempo requerido para realizar la verificación.

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Acknowledgment

The authors gratefully acknowledge the contribution of J. Moreno, Research Assistant at CINVESTAV–IPN, Guadalajara. Likewise, they would like to acknowledge Safelogic for allowing them to use the safelogic verifierfor the formal verification process of their code.

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