<?xml version="1.0" encoding="ISO-8859-1"?><article xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<front>
<journal-meta>
<journal-id>1665-6423</journal-id>
<journal-title><![CDATA[Journal of applied research and technology]]></journal-title>
<abbrev-journal-title><![CDATA[J. appl. res. technol]]></abbrev-journal-title>
<issn>1665-6423</issn>
<publisher>
<publisher-name><![CDATA[Universidad Nacional Autónoma de México, Instituto de Ciencias Aplicadas y Tecnología]]></publisher-name>
</publisher>
</journal-meta>
<article-meta>
<article-id>S1665-64232004000200005</article-id>
<title-group>
<article-title xml:lang="en"><![CDATA[Performance of a new bus assignment algorithm for an ATM switch fabric]]></article-title>
</title-group>
<contrib-group>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Sánchez]]></surname>
<given-names><![CDATA[J.]]></given-names>
</name>
<xref ref-type="aff" rid="A01"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Torres]]></surname>
<given-names><![CDATA[D.]]></given-names>
</name>
<xref ref-type="aff" rid="A02"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Ruiz]]></surname>
<given-names><![CDATA[E.]]></given-names>
</name>
<xref ref-type="aff" rid="A01"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Guzmán]]></surname>
<given-names><![CDATA[M.]]></given-names>
</name>
<xref ref-type="aff" rid="A02"/>
</contrib>
</contrib-group>
<aff id="A01">
<institution><![CDATA[,Centro de Investigación Científica y de Educación Superior de Ensenada Departamento de Electrónica y Telecomunicaciones ]]></institution>
<addr-line><![CDATA[Ensenada Baja California]]></addr-line>
<country>México</country>
</aff>
<aff id="A02">
<institution><![CDATA[,Instituto Politécnico Nacional Centro de Investigación y de Estudios Avanzados ]]></institution>
<addr-line><![CDATA[Guadalajara Jalisco]]></addr-line>
<country>México</country>
</aff>
<pub-date pub-type="pub">
<day>00</day>
<month>00</month>
<year>2004</year>
</pub-date>
<pub-date pub-type="epub">
<day>00</day>
<month>00</month>
<year>2004</year>
</pub-date>
<volume>2</volume>
<numero>2</numero>
<fpage>138</fpage>
<lpage>150</lpage>
<copyright-statement/>
<copyright-year/>
<self-uri xlink:href="http://www.scielo.org.mx/scielo.php?script=sci_arttext&amp;pid=S1665-64232004000200005&amp;lng=en&amp;nrm=iso"></self-uri><self-uri xlink:href="http://www.scielo.org.mx/scielo.php?script=sci_abstract&amp;pid=S1665-64232004000200005&amp;lng=en&amp;nrm=iso"></self-uri><self-uri xlink:href="http://www.scielo.org.mx/scielo.php?script=sci_pdf&amp;pid=S1665-64232004000200005&amp;lng=en&amp;nrm=iso"></self-uri><abstract abstract-type="short" xml:lang="en"><p><![CDATA[This paper presents the results of the performance evaluation, through analytical and simulation models, of a High Speed Packet Switch with a New Bus Assignment Algorithm, designed and developed at the Research and Advanced Studies Center of National Polytechnic Institute in Guadalajara, México (CINVESTAV-GDL). The analytical model is tested under two different arrival processes: Binomial and Poisson distributions. The simulation model is tested with two bus assignment algorithms: Fixed Start and Rotated Start . The performance parameters considered are: Cell Loss Rate, Delay and Throughput.]]></p></abstract>
<kwd-group>
<kwd lng="en"><![CDATA[ATM Switch]]></kwd>
<kwd lng="en"><![CDATA[Bus assignment algorithm]]></kwd>
<kwd lng="en"><![CDATA[Cell loss rate]]></kwd>
<kwd lng="en"><![CDATA[Poison arrivals]]></kwd>
<kwd lng="en"><![CDATA[Throughput]]></kwd>
</kwd-group>
</article-meta>
</front><body><![CDATA[  	    <p align="center"><font face="verdana" size="4"><b>Performance of a new bus assignment algorithm for an ATM switch fabric</b></font></p>     <p align="center">&nbsp;</p>  	    <p align="center"><b><font face="verdana" size="2">J. S&aacute;nchez<sup>1</sup>, D. Torres<sup>2</sup>, E. Ruiz<sup>1</sup> &amp; M. Guzm&aacute;n<sup>2</sup></font></b><font face="verdana" size="2"></font></p>     <p align="center">&nbsp;</p>  	    <p align="justify"><font face="verdana" size="2"><sup>1</sup>&nbsp;<i>CICESE, Depto. de Electr&oacute;nica y Telecomunicaciones, Km. 107 Carretera Tijuana&#45;Ensenada, Ensenada, B.C., 22860, M&eacute;xico.</i> Tel:(646)1744502&#45;06, Fax: (646)1750554, e&#45;mail: <a href="mailto:jasan@cicese.mx">jasan@cicese.mx</a></font></p>  	    <p align="justify"><font face="verdana" size="2"><sup>2</sup>&nbsp;<i>Centro de Investigaci&oacute;n y de Estudios Avanzados del IPN, Unidad Guadalajara, Prol. L&oacute;pez Mateos Sur 590, Guadalajara, Jal., M&eacute;xico.</i></font></p>     <p align="justify">&nbsp;</p>  	    <p align="justify"><font face="verdana" size="2">Received: May 24<sup>th</sup>, 2002.    <br> Accepted: February 19<sup>th</sup>, 2003. </font></p> 	    ]]></body>
<body><![CDATA[<p align="justify">&nbsp;</p> 	    <p align="justify"><font face="verdana" size="2"><b>Abstract</b></font></p>  	    <p align="justify"><font face="verdana" size="2">This paper presents the results of the performance evaluation, through analytical and simulation models, of a High Speed Packet Switch with a New Bus Assignment Algorithm, designed and developed at the Research and Advanced Studies Center of National Polytechnic Institute in Guadalajara, M&eacute;xico (CINVESTAV&#45;GDL). The analytical model is tested under two different arrival processes: Binomial and Poisson distributions. The simulation model is tested with two bus assignment algorithms: Fixed Start and Rotated Start . The performance parameters considered are: Cell Loss Rate, Delay and Throughput.</font></p>  	    <p align="justify"><font face="verdana" size="2"><b>Keywords:</b> ATM Switch, Bus assignment algorithm, Cell loss rate, Poison arrivals, Throughput.</font></p>     <p align="justify">&nbsp;</p>  	    <p align="justify"><font face="verdana" size="2"><a href="/pdf/jart/v2n2/v2n2a5.pdf" target="_blank">DESCARGAR ART&Iacute;CULO EN FORMATO PDF</a></font></p> 	    <p align="justify">&nbsp;</p>  	    <p align="justify"><font face="verdana" size="2"><b>References</b></font></p>  	    <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;1&#93; Nail, A., Nihat, S., Oguz, C. &amp; Sohraby K. An Advanced Teletraffic Analysis Package, IEEE Communication Magazine, 36, (8), 84&#45;87 1998.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4815671&pid=S1665-6423200400020000500001&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>  	    ]]></body>
<body><![CDATA[<!-- ref --><p align="justify"><font face="verdana" size="2">&#91;2&#93; Pitts, J.M. &amp; Schormans, J.A., <i>Introduction to ATM Design and Performance: With Application Analysis Software, </i>(John Wiley and Sons, England), 1996.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4815673&pid=S1665-6423200400020000500002&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2"> &#91;3&#93; Higginbottom, G. N. <i>Performance Evaluation of Communication Networks,</i> (Artech House Publishers, Norwood MA), First Edition, 1998.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4815675&pid=S1665-6423200400020000500003&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p> 	    <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;4&#93; Torres, D., Larios, A. &amp; Guzman, M., Routing Chip Based on a Modified Tree for ATM, IP and Ethernet: Hard/Software Co&#45;design, <i>Proceedings of<sup>:</sup> IEEEISCASS 99,</i> (IEEE, Orlando FL), 1, 427&#45;430 1999.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4815677&pid=S1665-6423200400020000500004&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p> 	    <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;5&#93; Torres, D., Gonz&aacute;lez, J., Guzman, M. &amp; Nu&ntilde;ez, L. A New Bus Assignment in a Designed Shared Bus Switch Fabric, <i>Proceedings of IEEE SSCASS</i> 99,(IEEE, Orlando FL), 1, 423&#45;426 1999.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4815679&pid=S1665-6423200400020000500005&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p> 	    <!-- ref --><p align="justify"><font face="verdana" size="2"> &#91;6&#93; Gonz&aacute;lez, J. <i>Architecture, Design and Implementation of a High Speed Cell Switch Fabric,</i> (CINVESTAV Guadalajara), M. Sc. Thesis, 1998.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4815681&pid=S1665-6423200400020000500006&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --> </font></p>     ]]></body>
<body><![CDATA[<!-- ref --><p align="justify"><font face="verdana" size="2">&#91;7&#93; Nunez, L., <i>Verification of the elements of a High Speed Cell Switch Fabric,</i> (CINVESTAV Guadalajara), M. Sc. Thesis, 2000.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4815683&pid=S1665-6423200400020000500007&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p>  	    <!-- ref --><p align="justify"><font face="verdana" size="2">&#91;8&#93; Hluchyj, M. G. &amp; Karol M.J., Queueing in High performance Packet Switching,IEEE JSAC 6, (9), 1587-1597 (1988). , Vol. 6, No. 9, 1988, pp: 1587-1597.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4815685&pid=S1665-6423200400020000500008&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font>	</p> 	    <!-- ref --><p align="justify"><font face="verdana" size="2">&#091;9&#093; Leonard, K., <i>Queueing Systems Volumen I: Theory,</i> (John Wiley and Sons, New York), First Edition, 1975.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4815687&pid=S1665-6423200400020000500009&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p> 	    <!-- ref --><p align="justify"><font face="verdana" size="2"> &#91;10&#93; Cooper, R., <i>Introduction to Queuing Theory,</i> (The Macmillan Company, New York), 1972.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4815689&pid=S1665-6423200400020000500010&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --></font></p> 	    <!-- ref --><p align="justify"><font face="verdana" size="2"> &#91;11&#93; Papoulis, A. <i>Probability, Random Variables and Stochastic Processes,</i> (Mc Graw Hill, USA), 666 1991.    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=4815691&pid=S1665-6423200400020000500011&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --> </font></p> 	    ]]></body>
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