<?xml version="1.0" encoding="ISO-8859-1"?><article xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<front>
<journal-meta>
<journal-id>1405-7743</journal-id>
<journal-title><![CDATA[Ingeniería, investigación y tecnología]]></journal-title>
<abbrev-journal-title><![CDATA[Ing. invest. y tecnol.]]></abbrev-journal-title>
<issn>1405-7743</issn>
<publisher>
<publisher-name><![CDATA[Universidad Nacional Autónoma de México, Facultad de Ingeniería]]></publisher-name>
</publisher>
</journal-meta>
<article-meta>
<article-id>S1405-77432020000400004</article-id>
<article-id pub-id-type="doi">10.22201/fi.25940732e.2020.21.4.032</article-id>
<title-group>
<article-title xml:lang="es"><![CDATA[Implementación digital basada en FPGA de la técnica PWM para el inversor multinivel en cascada]]></article-title>
<article-title xml:lang="en"><![CDATA[FPGA-Based Digital Implementation of PWM Technique for Cascaded Multilevel Inverter]]></article-title>
</title-group>
<contrib-group>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Valdez-Bahena]]></surname>
<given-names><![CDATA[Adolfo]]></given-names>
</name>
<xref ref-type="aff" rid="Aff"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[León-Aldaco]]></surname>
<given-names><![CDATA[Susana Estefany De]]></given-names>
</name>
<xref ref-type="aff" rid="Aff"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Aguayo-Alquicira]]></surname>
<given-names><![CDATA[Jesús]]></given-names>
</name>
<xref ref-type="aff" rid="Aff"/>
</contrib>
</contrib-group>
<aff id="Af1">
<institution><![CDATA[,Centro Nacional de Investigación y Desarrollo Tecnológico  ]]></institution>
<addr-line><![CDATA[Morelos ]]></addr-line>
<country>México</country>
</aff>
<aff id="Af2">
<institution><![CDATA[,Centro Nacional de Investigación y Desarrollo Tecnológico  ]]></institution>
<addr-line><![CDATA[Morelos ]]></addr-line>
<country>México</country>
</aff>
<aff id="Af3">
<institution><![CDATA[,Centro Nacional de Investigación y Desarrollo Tecnológico  ]]></institution>
<addr-line><![CDATA[Morelos ]]></addr-line>
<country>Mexico</country>
</aff>
<pub-date pub-type="pub">
<day>00</day>
<month>12</month>
<year>2020</year>
</pub-date>
<pub-date pub-type="epub">
<day>00</day>
<month>12</month>
<year>2020</year>
</pub-date>
<volume>21</volume>
<numero>4</numero>
<copyright-statement/>
<copyright-year/>
<self-uri xlink:href="http://www.scielo.org.mx/scielo.php?script=sci_arttext&amp;pid=S1405-77432020000400004&amp;lng=en&amp;nrm=iso"></self-uri><self-uri xlink:href="http://www.scielo.org.mx/scielo.php?script=sci_abstract&amp;pid=S1405-77432020000400004&amp;lng=en&amp;nrm=iso"></self-uri><self-uri xlink:href="http://www.scielo.org.mx/scielo.php?script=sci_pdf&amp;pid=S1405-77432020000400004&amp;lng=en&amp;nrm=iso"></self-uri><abstract abstract-type="short" xml:lang="es"><p><![CDATA[Resumen: El desarrollo de topologías de inversores multiniveles ha dado lugar a diversas técnicas de modulación de ancho de pulso, entre las más utilizadas se encuentran las que utilizan señales portadoras múltiples. Sin embargo, el inconveniente de la aplicación de este tipo de técnicas de modulación es que se hace necesario generar un gran número de señales de conmutación para todos los dispositivos semiconductores de potencia que componen el inversor. Los conjuntos de puertas programables en el campo son una herramienta poderosa que permite obtener estas señales de manera rápida y precisa. El propósito de este artículo es describir la metodología utilizada para generar digitalmente las señales de conmutación para un inversor multinivel utilizando una tarjeta de desarrollo tipo &#8220;arreglo de campos de compuertas programable&#8221;. El procedimiento utilizado se divide en dos programas: un script de Matlab y un código creado en Quartus II. El proceso de diseño presentado es fácil, rápido, flexible y aplicable a otras técnicas de modulación multiportadora. La técnica de modulación implementada en la tarjeta de desarrollo se verifica experimentalmente en un inversor multinivel en cascada trifásico para generar cinco niveles de tensión de salida con diferentes velocidades de modulación. Los resultados obtenidos experimentalmente se comparan con los obtenidos en la simulación con el software PSpice. El análisis de los resultados permite comprobar el correcto funcionamiento de la técnica de modulación aplicada.]]></p></abstract>
<abstract abstract-type="short" xml:lang="en"><p><![CDATA[Abstract: The development of multilevel inverter topologies has given rise to various pulse width modulation techniques, among the most used are those that use multiple carrier signals. However, the drawback of implementing this type of modulation techniques is that it is necessary to generate a large number of switching signals for all the power semiconductor devices that make up the inverter. Field-Programmable Gate Arrays are a powerful tool that allows these signals to be obtained quickly and accurately. The purpose of this article is to describe the methodology used for digitally generate the switching signals for a multilevel inverter using a Field-Programmable Gate Array. The procedure used is divided into two programs; a Matlab script and a code created in Quartus II. The design process presented is easy, fast, flexible and applicable to other multicarrier modulation techniques. The modulation technique implemented in the Field-Programmable Gate Array is experimentally verified in a three-phase cascaded multilevel inverter to generate five output voltage levels with different modulation rates. The results obtained experimentally are compared with those obtained in simulation using PSpice. The analysis of the results allows to check the correct functioning of the implemented modulation technique.]]></p></abstract>
<kwd-group>
<kwd lng="es"><![CDATA[Inversor multinivel en cascada]]></kwd>
<kwd lng="es"><![CDATA[FPGA]]></kwd>
<kwd lng="es"><![CDATA[Matlab]]></kwd>
<kwd lng="es"><![CDATA[técnica modulación por ancho de pulso]]></kwd>
<kwd lng="es"><![CDATA[Quartus II]]></kwd>
<kwd lng="en"><![CDATA[Cascaded Multilevel Inverter]]></kwd>
<kwd lng="en"><![CDATA[FPGA]]></kwd>
<kwd lng="en"><![CDATA[Matlab]]></kwd>
<kwd lng="en"><![CDATA[PWM technique]]></kwd>
<kwd lng="en"><![CDATA[Quartus II]]></kwd>
</kwd-group>
</article-meta>
</front><back>
<ref-list>
<ref id="B1">
<nlm-citation citation-type="book">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Gordillo]]></surname>
<given-names><![CDATA[J.]]></given-names>
</name>
</person-group>
<source><![CDATA[Compensación por medio de la modulación de la onda de salida de un inversor multinivel en cascada ante desbalances en las fuentes de alimentación]]></source>
<year>2011</year>
<publisher-loc><![CDATA[México ]]></publisher-loc>
<publisher-name><![CDATA[Centro Nacional de Investigación y Desarrollo Tecnológico]]></publisher-name>
</nlm-citation>
</ref>
<ref id="B2">
<nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Lakka]]></surname>
<given-names><![CDATA[M.]]></given-names>
</name>
<name>
<surname><![CDATA[Koutroulis]]></surname>
<given-names><![CDATA[E.]]></given-names>
</name>
<name>
<surname><![CDATA[Dollas]]></surname>
<given-names><![CDATA[A.]]></given-names>
</name>
</person-group>
<article-title xml:lang=""><![CDATA[Development of an FPGA-based SPWM generator for high switching frequency DC/AC inverters]]></article-title>
<source><![CDATA[IEEE Transactions on power electronics]]></source>
<year>2013</year>
<volume>29</volume>
<numero>1</numero>
<issue>1</issue>
<page-range>356-65</page-range></nlm-citation>
</ref>
<ref id="B3">
<nlm-citation citation-type="confpro">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Malinowski]]></surname>
<given-names><![CDATA[M.]]></given-names>
</name>
<name>
<surname><![CDATA[Stynski]]></surname>
<given-names><![CDATA[S.]]></given-names>
</name>
</person-group>
<source><![CDATA[Simulation of single-phase cascade multilevel PWM converters]]></source>
<year>2007</year>
<conf-name><![CDATA[ EUROCON 2007-The International Conference on "Computer as a Tool"]]></conf-name>
<conf-loc> </conf-loc>
</nlm-citation>
</ref>
<ref id="B4">
<nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Naderi]]></surname>
<given-names><![CDATA[R.]]></given-names>
</name>
<name>
<surname><![CDATA[Rahmati]]></surname>
<given-names><![CDATA[A.]]></given-names>
</name>
</person-group>
<article-title xml:lang=""><![CDATA[Phase-shifted carrier PWM technique for general cascaded inverters]]></article-title>
<source><![CDATA[IEEE Transactions on power electronics]]></source>
<year>2008</year>
<volume>23</volume>
<numero>3</numero>
<issue>3</issue>
<page-range>1257-69</page-range></nlm-citation>
</ref>
<ref id="B5">
<nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Palanivel]]></surname>
<given-names><![CDATA[P.]]></given-names>
</name>
<name>
<surname><![CDATA[Dash]]></surname>
<given-names><![CDATA[S. S.]]></given-names>
</name>
</person-group>
<article-title xml:lang=""><![CDATA[Analysis of THD and output voltage performance for cascaded multilevel inverter using carrier pulse width modulation techniques]]></article-title>
<source><![CDATA[IET Power Electronics]]></source>
<year>2011</year>
<volume>4</volume>
<numero>8</numero>
<issue>8</issue>
<page-range>951-8</page-range></nlm-citation>
</ref>
<ref id="B6">
<nlm-citation citation-type="">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Rajendra]]></surname>
<given-names><![CDATA[R.]]></given-names>
</name>
<name>
<surname><![CDATA[Chitra]]></surname>
<given-names><![CDATA[A.]]></given-names>
</name>
<name>
<surname><![CDATA[Meenakshi]]></surname>
<given-names><![CDATA[T.]]></given-names>
</name>
</person-group>
<source><![CDATA[Digital implementation of fpga based pwm generator for cascade h-bridge multilevel inverter]]></source>
<year>2009</year>
</nlm-citation>
</ref>
<ref id="B7">
<nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Rathore]]></surname>
<given-names><![CDATA[S.]]></given-names>
</name>
<name>
<surname><![CDATA[Kirar]]></surname>
<given-names><![CDATA[M. K.]]></given-names>
</name>
<name>
<surname><![CDATA[Bhardwaj]]></surname>
<given-names><![CDATA[S.]]></given-names>
</name>
</person-group>
<article-title xml:lang=""><![CDATA[Simulation of cascaded H-bridge multilevel inverter using PD, POD, APOD techniques]]></article-title>
<source><![CDATA[Electrical &amp; Computer Engineering: An International Journal (ECIJ)]]></source>
<year>2015</year>
<volume>4</volume>
<numero>3</numero>
<issue>3</issue>
<page-range>27-41</page-range></nlm-citation>
</ref>
<ref id="B8">
<nlm-citation citation-type="book">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Reyes]]></surname>
<given-names><![CDATA[Y.]]></given-names>
</name>
</person-group>
<source><![CDATA[Estudio del desempeño del conjunto motor-inversor multinivel en cascada trifásico]]></source>
<year>2018</year>
<publisher-loc><![CDATA[México ]]></publisher-loc>
<publisher-name><![CDATA[Centro Nacional de Investigación y Desarrollo Tecnológico]]></publisher-name>
</nlm-citation>
</ref>
<ref id="B9">
<nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Reyes]]></surname>
<given-names><![CDATA[Y.]]></given-names>
</name>
<name>
<surname><![CDATA[Aguayo]]></surname>
<given-names><![CDATA[J.]]></given-names>
</name>
<name>
<surname><![CDATA[De León]]></surname>
<given-names><![CDATA[S. E.]]></given-names>
</name>
<name>
<surname><![CDATA[Carrillo]]></surname>
<given-names><![CDATA[L. M.]]></given-names>
</name>
</person-group>
<article-title xml:lang=""><![CDATA[Comparative analysis of PD-PWM technique in the set: Multilevel Inverter-Induction motor]]></article-title>
<source><![CDATA[Ingeniería Investigación y Tecnología]]></source>
<year>2020</year>
<volume>XXI</volume>
<numero>1</numero>
<issue>1</issue>
<page-range>1-8</page-range></nlm-citation>
</ref>
<ref id="B10">
<nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Rodriguez]]></surname>
<given-names><![CDATA[J.]]></given-names>
</name>
<name>
<surname><![CDATA[Lai]]></surname>
<given-names><![CDATA[J.-S.]]></given-names>
</name>
<name>
<surname><![CDATA[Peng]]></surname>
<given-names><![CDATA[F. Z.]]></given-names>
</name>
</person-group>
<article-title xml:lang=""><![CDATA[Multilevel inverters: a survey of topologies, controls, and applications]]></article-title>
<source><![CDATA[IEEE Transactions on industrial electronics]]></source>
<year>2002</year>
<volume>49</volume>
<numero>4</numero>
<issue>4</issue>
<page-range>724-38</page-range></nlm-citation>
</ref>
<ref id="B11">
<nlm-citation citation-type="book">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Sanabria]]></surname>
<given-names><![CDATA[C. A.]]></given-names>
</name>
</person-group>
<source><![CDATA[Estrategia PWM implementada en un FPGA para aplicación en inversores multinivel]]></source>
<year>2004</year>
<publisher-loc><![CDATA[México ]]></publisher-loc>
<publisher-name><![CDATA[Centro Nacional de Investigación y Desarrollo Tecnológico]]></publisher-name>
</nlm-citation>
</ref>
<ref id="B12">
<nlm-citation citation-type="book">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Sánchez]]></surname>
<given-names><![CDATA[C. A. S.]]></given-names>
</name>
</person-group>
<source><![CDATA[Estrategia PWM implementada en un FPGA para aplicación en inversores multinivel]]></source>
<year>2004</year>
<publisher-loc><![CDATA[México ]]></publisher-loc>
<publisher-name><![CDATA[Centro Nacional de Investigación y Desarrollo Tecnológico]]></publisher-name>
</nlm-citation>
</ref>
</ref-list>
</back>
</article>
