New High–Performance Full Adders Using an Alternative Logic Structure
Nuevos sumadores de alto desempeño utilizando una estructura lógica alternativa
Mónico Linares Aranda1 and Mariano Aguirre Hernández2
1 Instituto Nacional de Astrofísica, Óptica y Electrónica Apartado postal 51 y 216, C.P. 72000, Puebla, Pue. México. E mail: mlinares@inaoep.mx
]]> 2 Intel Corporation, Communications Research Center, México. Email: mariano.aguirre@intel.com
Article received on March 24, 2009
Accepted on October 20, 2009
Abstract
This paper presents two new high–speed low–power 1–bit full–adder cells using an alternative logic structure, and the logic styles DPL and SR–CPL. The adders were designed using electrical parameters of a 0.35µm Complementary Metal–Oxide–Semiconductor (CMOS) process, and were compared with various adders published previously, with regards of power–delay product. To validate the performance simulation results of one of the proposed adders, an 8–bits pipelined multiplier was fabricated using a 0.35µm CMOS technology, and it showed to provide superior performance.
Keywords: Full–adder, Low–power, Multiplier, Pipeline.
Resumen
]]> En este artículo se presentan dos nuevos sumadores de 1–bit de alta velocidad y bajo consumo de potencia, utilizando en su diseño una estructura lógica alternativa y los estilos lógicos de circuitos DPL y SR–CPL. Los nuevos sumadores fueron comparados con diversos sumadores recientemente publicados en la literatura considerando el producto potencia–retardo, principal figura de mérito de circuitos aritméticos. Con el fin de validar los resultados obtenidos de simulación, uno de los sumadores fue aplicado al diseño y fabricación de un multiplicador en "pipeline" de 8–bits utilizando la tecnología CMOS de 0.35µm. Los resultados experimentales obtenidos mostraron un desempeño superior.Palabras clave: Sumador completo, Baja potencia, Multiplicador, Pipeline.
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Acknowledgment
This work was partially supported by Conacyt–Mexico under grant #51511–Y and scholarship #112784.
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