<?xml version="1.0" encoding="ISO-8859-1"?><article xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<front>
<journal-meta>
<journal-id>1870-3542</journal-id>
<journal-title><![CDATA[Revista mexicana de física E]]></journal-title>
<abbrev-journal-title><![CDATA[Rev. mex. fís. E]]></abbrev-journal-title>
<issn>1870-3542</issn>
<publisher>
<publisher-name><![CDATA[Sociedad Mexicana de Física]]></publisher-name>
</publisher>
</journal-meta>
<article-meta>
<article-id>S1870-35422007000200001</article-id>
<title-group>
<article-title xml:lang="en"><![CDATA[Basic circuits to design switched-based DC-DC converters]]></article-title>
</title-group>
<contrib-group>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Sandoval-Ibarra]]></surname>
<given-names><![CDATA[F]]></given-names>
</name>
<xref ref-type="aff" rid="A01"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Mercado-Moreno]]></surname>
<given-names><![CDATA[J.R]]></given-names>
</name>
<xref ref-type="aff" rid="A02"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Urióstegui-Vázquez]]></surname>
<given-names><![CDATA[L.H]]></given-names>
</name>
<xref ref-type="aff" rid="A02"/>
</contrib>
</contrib-group>
<aff id="A01">
<institution><![CDATA[,CINVESTAV-Guadalajara Unit  ]]></institution>
<addr-line><![CDATA[Guadalajara Jal]]></addr-line>
<country>México</country>
</aff>
<aff id="A02">
<institution><![CDATA[,Mabe, Investigación y Desarrollo  ]]></institution>
<addr-line><![CDATA[Querétaro Qro]]></addr-line>
<country>México</country>
</aff>
<pub-date pub-type="pub">
<day>00</day>
<month>12</month>
<year>2007</year>
</pub-date>
<pub-date pub-type="epub">
<day>00</day>
<month>12</month>
<year>2007</year>
</pub-date>
<volume>53</volume>
<numero>2</numero>
<fpage>128</fpage>
<lpage>133</lpage>
<copyright-statement/>
<copyright-year/>
<self-uri xlink:href="http://www.scielo.org.mx/scielo.php?script=sci_arttext&amp;pid=S1870-35422007000200001&amp;lng=en&amp;nrm=iso"></self-uri><self-uri xlink:href="http://www.scielo.org.mx/scielo.php?script=sci_abstract&amp;pid=S1870-35422007000200001&amp;lng=en&amp;nrm=iso"></self-uri><self-uri xlink:href="http://www.scielo.org.mx/scielo.php?script=sci_pdf&amp;pid=S1870-35422007000200001&amp;lng=en&amp;nrm=iso"></self-uri><abstract abstract-type="short" xml:lang="en"><p><![CDATA[The purpose of this paper is twofold. On one hand, basics on switched circuits for designing a DC-DC converter are presented and, on the other hand, power electronics definitions associated with simple electrical networks are mentioned. In the analysis of these networks, it is necessary to take into account not only converters' non-idealities but also how to minimize power losses. Since power losses may be minimized by increasing the clock frequency of switched-based converters, experimental results of basic clock generators are presented. These generators were implemented with low-cost components]]></p></abstract>
<abstract abstract-type="short" xml:lang="es"><p><![CDATA[El propósito de este artículo es doble. Por un lado, se presentan conceptos básicos de circuitos conmutados para diseñar un convertidor CD-CD y, por el otro, se rescatan definiciones de electrónica de potencia asociadas a redes eléctricas simples. En el análisis de esas redes es necesario tomar en cuenta no solo las no idealidades de los convertidores sino también cómo minimizar pérdidas de potencia. Porque las perdidas de potencia pueden ser minimizadas aumentando la frecuencia de reloj de los convertidores conmutados, se presentan resultados experimentales de generadores de reloj. Estos circuitos fueron implementados con componentes de bajo costo]]></p></abstract>
<kwd-group>
<kwd lng="en"><![CDATA[Electric circuits]]></kwd>
<kwd lng="en"><![CDATA[power electronics]]></kwd>
<kwd lng="en"><![CDATA[oscillators]]></kwd>
<kwd lng="es"><![CDATA[Circuitos eléctricos]]></kwd>
<kwd lng="es"><![CDATA[electrónica de potencia]]></kwd>
<kwd lng="es"><![CDATA[osciladores]]></kwd>
</kwd-group>
</article-meta>
</front><body><![CDATA[ <p align="justify"><font face="verdana" size="4">Ense&ntilde;anza</font></p>     <p align="justify"><font face="verdana" size="2">&nbsp;</font></p>     <p align="center"><font face="verdana" size="4"><b>Basic circuits to design switched&#150;based DC&#150;DC converters</b></font></p>     <p align="justify"><font face="verdana" size="2">&nbsp;</font></p>     <p align="center"><font face="verdana" size="2"><b>F. Sandoval&#150;Ibarra&ordf;, J.R. Mercado&#150;Moreno<sup>b</sup> and L.H. Uri&oacute;stegui&#150;V&aacute;zquez<sup>b</sup></b></font></p>     <p align="justify"><font face="verdana" size="2">&nbsp;</font></p>     <p align="justify"><font face="verdana" size="2"><i>&ordf; CINVESTAV&#150;Guadalajara Unit, Prol. Av. L&oacute;pez&#150;Mateos Sur, 590, Guadalajara Jal, M&eacute;xico, </i>e&#150;mail: <a href="mailto:sandoval@cts-design.com">sandoval@cts-design.com</a></font></p>     <p align="justify"><font face="verdana" size="2"><i><sup>b</sup> Mabe, Investigaci&oacute;n y Desarrollo, Parque Industrial Jurica, 76120 Quer&eacute;taro Qro., M&eacute;xico, </i>e&#150;mail: <a href="mailto:juan.mercado@mabe.com.mx">juan.mercado@mabe.com.mx</a>, <a href="mailto:luis.uriostegui@mabe.com.mx">luis.uriostegui@mabe.com.mx</a></font></p>     <p align="justify"><font face="verdana" size="2">&nbsp;</font></p>     <p align="justify"><font face="verdana" size="2">Recibido el 28 de junio de 2005    ]]></body>
<body><![CDATA[<br> Aceptado el 26 de marzo de 2007</font></p>     <p align="justify"><font face="verdana" size="2">&nbsp;</font></p>     <p align="justify"><font face="verdana" size="2"><b>Abstract</b></font></p>     <p align="justify"><font face="verdana" size="2">The purpose of this paper is twofold. On one hand, basics on switched circuits for designing a DC&#150;DC converter are presented and, on the other hand, power electronics definitions associated with simple electrical networks are mentioned. In the analysis of these networks, it is necessary to take into account not only converters' non&#150;idealities but also how to minimize power losses. Since power losses may be minimized by increasing the clock frequency of switched&#150;based converters, experimental results of basic clock generators are presented. These generators were implemented with low&#150;cost components.</font></p>     <p align="justify"><font face="verdana" size="2"><b>Keywords: </b>Electric circuits; power electronics; oscillators.</font></p>     <p align="justify"><font face="verdana" size="2">&nbsp;</font></p>     <p align="justify"><font face="verdana" size="2"><b>Resumen</b></font></p>     <p align="justify"><font face="verdana" size="2">El prop&oacute;sito de este art&iacute;culo es doble. Por un lado, se presentan conceptos b&aacute;sicos de circuitos conmutados para dise&ntilde;ar un convertidor CD&#150;CD y, por el otro, se rescatan definiciones de electr&oacute;nica de potencia asociadas a redes el&eacute;ctricas simples. En el an&aacute;lisis de esas redes es necesario tomar en cuenta no solo las no idealidades de los convertidores sino tambi&eacute;n c&oacute;mo minimizar p&eacute;rdidas de potencia. Porque las perdidas de potencia pueden ser minimizadas aumentando la frecuencia de reloj de los convertidores conmutados, se presentan resultados experimentales de generadores de reloj. Estos circuitos fueron implementados con componentes de bajo costo.</font></p>     <p align="justify"><font face="verdana" size="2"><b>Descriptores: </b>Circuitos el&eacute;ctricos; electr&oacute;nica de potencia; osciladores.</font></p>     <p align="justify"><font face="verdana" size="2">&nbsp;</font></p>     ]]></body>
<body><![CDATA[<p align="justify"><font face="verdana" size="2">PACS: 84.30.&#150;r; 84.30.Jc; 84.30.Ng</font></p>     <p align="justify"><font face="verdana" size="2">&nbsp;</font></p>     <p align="justify"><font face="verdana" size="2"><a href="/pdf/rmfe/v53n2/v53n2a1.pdf" target="_blank">DESCARGAR ART&Iacute;CULO EN FORMATO PDF</a></font></p>     <p align="justify"><font face="verdana" size="2">&nbsp;</font></p>     <p align="justify"><font face="verdana" size="2"><b>Acknowledgments</b></font></p>     <p align="justify"><font face="verdana" size="2">Authors wish to thank the anonymous reviewer for his helpful comments and critical review.</font></p>     <p align="justify"><font face="verdana" size="2">&nbsp;</font></p>     <p align="justify"><font face="verdana" size="2"><b>References</b></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">1. F. Callias, F.H. Salchli, and D. Girard, <i>IEEE Journal of Solid&#150;State Circuits </i><b>24</b> (1989).</font>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=8447714&pid=S1870-3542200700020000100001&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --><!-- ref --><p align="justify"><font face="verdana" size="2">2. L.S.Y. Wong <i>et al., IEEE J. of Solid&#150;State Circuits </i>39 (2004) 2446.</font>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=8447715&pid=S1870-3542200700020000100002&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --><!-- ref --><p align="justify"><font face="verdana" size="2">3. K. Lee, S.J. Lee, and H.J. Yoo, <i>IEEE Trans. on VLSI Sys. </i><b>14</b> (2006) 148.</font>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=8447716&pid=S1870-3542200700020000100003&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --><!-- ref --><p align="justify"><font face="verdana" size="2">4. V. Litivsky, M. Saviae, and Z. Mraearica, <i>HAIT J. of Sc. and Eng. B. </i><b>2</b> (2005) 476.</font>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=8447717&pid=S1870-3542200700020000100004&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --><!-- ref --><p align="justify"><font face="verdana" size="2">5. E. Vargas&#150;Calder&oacute;n and M.S. thesis, CINVESTAV&#150;Guadalajara Unit, Jalisco, M&eacute;xico, 2005 (in Spanish).</font>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=8447718&pid=S1870-3542200700020000100005&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --><!-- ref --><p align="justify"><font face="verdana" size="2">6. J. Terry <i>et al, IEEE J. of Solid&#150;State Circuits </i><b>SC&#150;12 </b>(1977) 592.</font>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=8447719&pid=S1870-3542200700020000100006&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --><!-- ref --><p align="justify"><font face="verdana" size="2">7. F. Sandoval&#150;Ibarra and E. Montoya&#150;Su&aacute;rez, <i>Rev. Mex. F&iacute;s. E </i><b>50</b> (2004) 114.</font>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=8447720&pid=S1870-3542200700020000100007&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --><!-- ref --><p align="justify"><font face="verdana" size="2">8. R.S. Muller and  T.I. Kamins, <i>Electr&oacute;nica de los Dispositivos para Circuitos Integrados, </i>1st edition (LIMUSA, M&eacute;xico, 1982) p. 454.</font>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=8447721&pid=S1870-3542200700020000100008&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --> ]]></body><back>
<ref-list>
<ref id="B1">
<label>1</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Callias]]></surname>
<given-names><![CDATA[F]]></given-names>
</name>
<name>
<surname><![CDATA[Salchli]]></surname>
<given-names><![CDATA[F.H]]></given-names>
</name>
<name>
<surname><![CDATA[Girard]]></surname>
<given-names><![CDATA[D]]></given-names>
</name>
</person-group>
<source><![CDATA[IEEE Journal of Solid-State Circuits]]></source>
<year>1989</year>
<numero>24</numero>
<issue>24</issue>
</nlm-citation>
</ref>
<ref id="B2">
<label>2</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Wong]]></surname>
<given-names><![CDATA[L.S.Y]]></given-names>
</name>
</person-group>
<source><![CDATA[IEEE J. of Solid-State Circuits]]></source>
<year>2004</year>
<numero>39</numero>
<issue>39</issue>
<page-range>2446</page-range></nlm-citation>
</ref>
<ref id="B3">
<label>3</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Lee]]></surname>
<given-names><![CDATA[K]]></given-names>
</name>
<name>
<surname><![CDATA[Lee]]></surname>
<given-names><![CDATA[S.J]]></given-names>
</name>
<name>
<surname><![CDATA[Yoo]]></surname>
<given-names><![CDATA[H.J]]></given-names>
</name>
</person-group>
<source><![CDATA[IEEE Trans. on VLSI Sys]]></source>
<year>2006</year>
<numero>14</numero>
<issue>14</issue>
<page-range>148</page-range></nlm-citation>
</ref>
<ref id="B4">
<label>4</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Litivsky]]></surname>
<given-names><![CDATA[V]]></given-names>
</name>
<name>
<surname><![CDATA[Saviae]]></surname>
<given-names><![CDATA[M]]></given-names>
</name>
<name>
<surname><![CDATA[Mraearica]]></surname>
<given-names><![CDATA[Z]]></given-names>
</name>
</person-group>
<source><![CDATA[HAIT J. of Sc. and Eng. B]]></source>
<year>2005</year>
<numero>2</numero>
<issue>2</issue>
<page-range>476</page-range></nlm-citation>
</ref>
<ref id="B5">
<label>5</label><nlm-citation citation-type="">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Vargas-Calderón]]></surname>
<given-names><![CDATA[E]]></given-names>
</name>
</person-group>
<source><![CDATA[]]></source>
<year></year>
</nlm-citation>
</ref>
<ref id="B6">
<label>6</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Terry]]></surname>
<given-names><![CDATA[J]]></given-names>
</name>
</person-group>
<source><![CDATA[IEEE J. of Solid-State Circuits]]></source>
<year>1977</year>
<numero>SC-12</numero>
<issue>SC-12</issue>
<page-range>592</page-range></nlm-citation>
</ref>
<ref id="B7">
<label>7</label><nlm-citation citation-type="journal">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Sandoval-Ibarra]]></surname>
<given-names><![CDATA[F]]></given-names>
</name>
<name>
<surname><![CDATA[Montoya-Suárez]]></surname>
<given-names><![CDATA[E]]></given-names>
</name>
</person-group>
<source><![CDATA[Rev. Mex. Fís. E]]></source>
<year>2004</year>
<numero>50</numero>
<issue>50</issue>
<page-range>114</page-range></nlm-citation>
</ref>
<ref id="B8">
<label>8</label><nlm-citation citation-type="book">
<person-group person-group-type="author">
<name>
<surname><![CDATA[Muller]]></surname>
<given-names><![CDATA[R.S]]></given-names>
</name>
<name>
<surname><![CDATA[Kamins]]></surname>
<given-names><![CDATA[T.I]]></given-names>
</name>
</person-group>
<source><![CDATA[Electrónica de los Dispositivos para Circuitos Integrados]]></source>
<year>1982</year>
<edition>1</edition>
<page-range>454</page-range><publisher-name><![CDATA[LIMUSA]]></publisher-name>
</nlm-citation>
</ref>
</ref-list>
</back>
</article>
