<?xml version="1.0" encoding="ISO-8859-1"?><article xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<front>
<journal-meta>
<journal-id>1405-5546</journal-id>
<journal-title><![CDATA[Computación y Sistemas]]></journal-title>
<abbrev-journal-title><![CDATA[Comp. y Sist.]]></abbrev-journal-title>
<issn>1405-5546</issn>
<publisher>
<publisher-name><![CDATA[Instituto Politécnico Nacional, Centro de Investigación en Computación]]></publisher-name>
</publisher>
</journal-meta>
<article-meta>
<article-id>S1405-55462005000400004</article-id>
<title-group>
<article-title xml:lang="en"><![CDATA[Computing Symbolic Expressions in Analog Circuits Using Nullors]]></article-title>
<article-title xml:lang="es"><![CDATA[Cálculo de Expresiones Simbólicas en Circuitos Analógicos usando Anuladores]]></article-title>
</title-group>
<contrib-group>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Tlelo Cuautle]]></surname>
<given-names><![CDATA[Esteban]]></given-names>
</name>
<xref ref-type="aff" rid="A01"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Carlos]]></surname>
<given-names><![CDATA[Sánchez López]]></given-names>
</name>
<xref ref-type="aff" rid="A02"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Sandoval Ibarra]]></surname>
<given-names><![CDATA[Federico]]></given-names>
</name>
<xref ref-type="aff" rid="A03"/>
</contrib>
</contrib-group>
<aff id="A01">
<institution><![CDATA[,INAOE Department of Electronics ]]></institution>
<addr-line><![CDATA[Tonantzintla Puebla]]></addr-line>
<country>México</country>
</aff>
<aff id="A02">
<institution><![CDATA[,Instituto Tecnológico de Puebla  ]]></institution>
<addr-line><![CDATA[ ]]></addr-line>
</aff>
<aff id="A03">
<institution><![CDATA[,CINVESTAV  ]]></institution>
<addr-line><![CDATA[Guadalajara ]]></addr-line>
</aff>
<pub-date pub-type="pub">
<day>00</day>
<month>12</month>
<year>2005</year>
</pub-date>
<pub-date pub-type="epub">
<day>00</day>
<month>12</month>
<year>2005</year>
</pub-date>
<volume>9</volume>
<numero>2</numero>
<fpage>119</fpage>
<lpage>132</lpage>
<copyright-statement/>
<copyright-year/>
<self-uri xlink:href="http://www.scielo.org.mx/scielo.php?script=sci_arttext&amp;pid=S1405-55462005000400004&amp;lng=en&amp;nrm=iso"></self-uri><self-uri xlink:href="http://www.scielo.org.mx/scielo.php?script=sci_abstract&amp;pid=S1405-55462005000400004&amp;lng=en&amp;nrm=iso"></self-uri><self-uri xlink:href="http://www.scielo.org.mx/scielo.php?script=sci_pdf&amp;pid=S1405-55462005000400004&amp;lng=en&amp;nrm=iso"></self-uri><abstract abstract-type="short" xml:lang="en"><p><![CDATA[A novel method is introduced to compute symbolic expressions in analog circuits modeled by nullors. The proposed method is based on the formulation of a compact system of equations (CSEs) by manipulation of data-structures, which highly improves traditional symbolic-methods. It is demonstrated that by modeling all active devices using nullors, the CSEs is easily formulated by manipulation of both the nullor and admittance interconnection-relationships. Several examples leads us to conclude on the suitability of the proposed symbolic-method to be incorporated within a symbolic simulator.]]></p></abstract>
<abstract abstract-type="short" xml:lang="es"><p><![CDATA[Se presenta un nuevo método para calcular expresiones simbólicas en circuitos analógicos modelados con anuladores (nullors). El método propuesto se basa en la formulación de un sistema de ecuaciones compacto (SEC), a través de la manipulación de estructuras de datos, lo cual mejora notablemente los métodos simbólicos tradicionales. Se demuestra que modelando todos los dispositivos activos usando nullors, el SEC se formula fácilmente por manipulación de las relaciones de interconexión del nullor y admitancias. Algunos ejemplos conducen a concluir en la confiabilidad del método simbólico propuesto para incorporarlo dentro de un simulador simbólico.]]></p></abstract>
<kwd-group>
<kwd lng="en"><![CDATA[Symbolic analysis]]></kwd>
<kwd lng="en"><![CDATA[Modeling and simulation]]></kwd>
<kwd lng="en"><![CDATA[Circuit theory]]></kwd>
<kwd lng="en"><![CDATA[Data structures]]></kwd>
<kwd lng="en"><![CDATA[Nullor]]></kwd>
<kwd lng="es"><![CDATA[Análisis simbólico]]></kwd>
<kwd lng="es"><![CDATA[Modelado y simulación]]></kwd>
<kwd lng="es"><![CDATA[Teoría de circuitos]]></kwd>
<kwd lng="es"><![CDATA[Estructura de datos]]></kwd>
<kwd lng="es"><![CDATA[Anulador]]></kwd>
</kwd-group>
</article-meta>
</front><body><![CDATA[ <p align="justify"><font face="verdana" size="4">Art&iacute;culos</font></p>     <p align="justify"><font face="verdana" size="2">&nbsp;</font></p>     <p align="center"><font face="verdana" size="4"><b>Computing Symbolic Expressions in Analog Circuits Using Nullors</b></font></p>     <p align="center"><font face="verdana" size="2">&nbsp;</font></p>     <p align="center"><font face="verdana" size="4"><i>C&aacute;lculo de Expresiones Simb&oacute;licas en Circuitos Anal&oacute;gicos usando Anuladores</i></font></p>     <p align="center"><font face="verdana" size="2">&nbsp;</font></p>     <p align="center"><font face="verdana" size="2"><b>Esteban Tlelo Cuautle<sup>1</sup><sup>,2</sup>, Carlos S&aacute;nchez L&oacute;pez<sup>1</sup> and Federico Sandoval Ibarra<sup>3</sup></b></font></p>     <p align="center"><font face="verdana" size="2">&nbsp;</font></p>     <p align="center"><font face="verdana" size="2"><i>1 INAOE, Department of Electronics,    <br>   Luis Enrique Erro No. 1, Tonantzintla, Puebla. 72000 M&eacute;xico.    ]]></body>
<body><![CDATA[<br> Tel/Fax: +52&#150;222&#150;2470517    <br> </i><a href="mailto:e.tlelo@ieee.org">e.tlelo@ieee.org</a>, <a href="mailto:csanchez@inaoep.mx">csanchez@inaoep.mx    <br> </a><A href=http://www.inaoep.mx target="_blank">http://www.inaoep.mx</A></font></p>     <p align="center"><font face="verdana" size="2"><i>2 Instituto Tecnol&oacute;gico de Puebla</i></font></p>     <p align="center"><font face="verdana" size="2"><i>3 CINVESTAV, Guadalajara Unit,    <br> </i><a href="mailto:sandoval@cts-design.com">sandoval@cts&#150;design.com</a></font></p>     <p align="center"><font face="verdana" size="2">&nbsp;</font></p>     <p align="center"><font face="verdana" size="2"><u>Article received on July 14, 2003; accepted en July 08, 2005</u></font></p>     <p align="center"><font face="verdana" size="2">&nbsp;</font></p>     <p align="justify"><font face="verdana" size="2"><b>Abstract</b></font></p>     ]]></body>
<body><![CDATA[<p align="justify"><font face="verdana" size="2">A novel method is introduced to compute symbolic expressions in analog circuits modeled by nullors. The proposed method is based on the formulation of a compact system of equations (CSEs) by manipulation of data&#150;structures, which highly improves traditional symbolic&#150;methods. It is demonstrated that by modeling all active devices using nullors, the CSEs is easily formulated by manipulation of both the nullor and admittance interconnection&#150;relationships. Several examples leads us to conclude on the suitability of the proposed symbolic&#150;method to be incorporated within a symbolic simulator.</font></p>     <p align="justify"><font face="verdana" size="2"><b>Keywords: </b>Symbolic analysis, Modeling and simulation, Circuit theory, Data structures, Nullor.</font></p>     <p align="justify"><font face="verdana" size="2">&nbsp;</font></p>     <p align="justify"><font face="verdana" size="2"><b>Resumen</b></font></p>     <p align="justify"><font face="verdana" size="2">Se presenta un nuevo m&eacute;todo para calcular expresiones simb&oacute;licas en circuitos anal&oacute;gicos modelados con anuladores (nullors). El m&eacute;todo propuesto se basa en la formulaci&oacute;n de un sistema de ecuaciones compacto (SEC), a trav&eacute;s de la manipulaci&oacute;n de estructuras de datos, lo cual mejora notablemente los m&eacute;todos simb&oacute;licos tradicionales. Se demuestra que modelando todos los dispositivos activos usando nullors, el SEC se formula f&aacute;cilmente por manipulaci&oacute;n de las relaciones de interconexi&oacute;n del nullor y admitancias. Algunos ejemplos conducen a concluir en la confiabilidad del m&eacute;todo simb&oacute;lico propuesto para incorporarlo dentro de un simulador simb&oacute;lico.</font></p>     <p align="justify"><font face="verdana" size="2"><b>Palabras Clave: </b>An&aacute;lisis simb&oacute;lico, Modelado y simulaci&oacute;n, Teor&iacute;a de circuitos, Estructura de datos, Anulador.</font></p>     <p align="justify">&nbsp;</p>     <p align="justify"><font face="verdana" size="2"><a href="/pdf/cys/v9n2/v9n2a4.pdf" target="_blank">DESCARGA ARTICULO EN FORMATO PDF</a></font></p>     <p align="justify"><font face="verdana" size="2">&nbsp;</font></p>     <p align="justify"><font face="verdana" size="2"><b>Acknowledgment</b></font></p>     ]]></body>
<body><![CDATA[<p align="justify"><font face="verdana" size="2">This work was supported in part by CONACyT/MEXICO under project number 40321, and CoSNET/MEXICO under project number 454.03p.</font></p>     <p align="justify"><font face="verdana" size="2">&nbsp;</font></p>     <p align="justify"><font face="verdana" size="2"><b>References</b></font></p>     <!-- ref --><p align="justify"><font face="verdana" size="2">1. <b>Cabeza, R.;  and Carlosena, A., </b>"On the use of symbolic analyzers in circuit synthesis," <i>Analog Integrated Circuits and Signal Processing, </i>25: 67&#150;75 (2000).</font>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=2039625&pid=S1405-5546200500040000400001&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --><!-- ref --><p align="justify"><font face="verdana" size="2">2. <b>Chua, Leon O.; and Lin, Pen&#150;Min, </b><i>Computer&#150;aided analysis of electronic circuits, </i>(Prentice Hall, 1975).</font>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=2039626&pid=S1405-5546200500040000400002&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --><!-- ref --><p align="justify"><font face="verdana" size="2">3. <b>Fern&aacute;ndez, F.V. et al., </b><i>Symbolic Analysis Techniques: Applications to Analog Design Automation, </i>(IEEE Press, 1998).</font>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=2039627&pid=S1405-5546200500040000400003&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --><!-- ref --><p align="justify"><font face="verdana" size="2">4. <b>Floberg, Henrik, </b><i>Symbolic analysis in analog integrated circuit design, </i>(Kluwer Academic Publishers, 1997).</font>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[&#160;<a href="javascript:void(0);" onclick="javascript: window.open('/scielo.php?script=sci_nlinks&ref=2039628&pid=S1405-5546200500040000400004&lng=','','width=640,height=500,resizable=yes,scrollbars=1,menubar=yes,');">Links</a>&#160;]<!-- end-ref --><!-- ref --><p align="justify"><font face="verdana" size="2">5. <b>Randall, Geiger L.; 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