Implementation of a 10.24 GS/s 12-bit Optoelectronics Analog-to-Digital Converter Based on a Polyphase Demultiplexing Architecture

 

C. Villa-Angulo*¹, I. O. Hernandez-Fuentes², R. Villa-Angulo³, S. E. Ahumada-Valdez⁴, R. A. Ramos-Irigoyen⁵, E. Donkor⁶

 

¹ Instituto de Ingeniería Universidad Autónoma de Baja California Mexicali, B. C., México. *villac@uabc.edu.mx.

² Instituto de Ingeniería Universidad Autónoma de Baja California Mexicali, B. C., México.

³ Instituto de Ingeniería Universidad Autónoma de Baja California Mexicali, B. C., México.

⁴ Instituto de Ingeniería Universidad Autónoma de Baja California Mexicali, B. C., México.

⁵ Instituto de Ingeniería Universidad Autónoma de Baja California Mexicali, B. C., México.

⁶ Department of Electrical & Computer Engineering University of Connecticut Storrs, CT., USA.

 

ABSTRACT

In this paper we present the practical implementation of a high-speed polyphase sampling and demultiplexing architecture for optoelectronics analog-to-digital converters (OADCs). The architecture consists of a one-stage divideby-eight decimator circuit where optically-triggered samplers are cascaded to sample an analog input signal, and demultiplex different phases of the sampled signal to yield low data rate for electronic quantization. Electrical-in to electrical-out data format is maintained through the sampling, demultiplexing and quantization processes of the architecture thereby avoiding the need for electrical-to-optical and optical-to-electrical signal conversions. We experimentally demonstrate a 10.24 giga samples per second (GS/s), 12-bit resolution OADC system comprising the optically-triggered sampling circuits integrated with commercial electronic quantizers. Measurements performed on the OADC yielded an effective bit resolution (ENOB) of 10.3 bits, spurious free dynamic range (SFDR) of -32 dB and signal-to-noise and distortion ratio (SNDR) of 63.7 dB.

Keywords: optoelectronics analog-to-digital converter (ADC), poly-phase conversion scheme, self-synchronized sampling, demultiplexing process.

 

RESUMEN

En este artículo se presenta la implementación de una arquitectura de muestreo y demultiplexación polifásica para implementarse en convertidores analógico digitales optoelectrónicos de alta velocidad (OADCs). La arquitectura consta de circuitos muestreadores activados ópticamente conectados en cascada. La arquitectura muestrea una señal analógica y posteriormente demultiplexa diferentes muestras (canaliza) para reducir la velocidad de repetición de las mismas y así la cuantización pueda realizarse con circuitos electrónicos de baja velocidad. Una característica importante de esta arquitectura es que la señal analógica es conservada en el dominio eléctrico durante el proceso de muestreo, demultiplexación y cuantización, evitando la necesidad de los procesos de conversión de eléctrica a óptica y de óptica a eléctrica comúnmente usados en OADCs. Experimentalmente se implementó un sistema OADC de 10.24 giga muestras por segundo (GM/s) con 12 bits de resolución. Mediciones demuestran una resolución efectiva (ENOB) de 10.3 bits, rango dinámico libre de espurios (SFDR) de -32 dB, y señal a ruido y distorsión (SNDR) de 63.7 dB.

 

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