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Ingeniería, investigación y tecnología
On-line version ISSN 2594-0732Print version ISSN 1405-7743
Ing. invest. y tecnol. vol.11 n.3 Ciudad de México Jul./Sep. 2010
Electrical Parameters Extraction of CMOS FloatingGate Inverters
Extracción de parámetros eléctricos de inversores CMOS de compuerta flotante
MolinarSolís J.E.1, PoncePonce V.H.2, R.Z. GarcíaLozano3, DíazSánchez A.4 y RochaPérez J.M.5
1 Universidad Autónoma del Estado de México, Email: Jemolinars@uaemex.mx
2 Centro de Investigación en Computación, Instituto Politécnico Nacional, México, Email: vponce@cic.ipn.mx
3 Universidad Autónoma del Estado de México, Email: zolagarcia@yahoo.com
4 Instituto Nacional de Astrofísica, Óptica y Electrónica INAOE, Tonantzintla, Puebla, Email: adiazsan@inaoep.mx
5 Instituto Nacional de Astrofísica, Óptica y Electrónica INAOE, Tonantzintla, Puebla, Email: jmr@inaoep.mx
Recibido: septiembre de 2008
Aceptado: julio de 2009
Abstract
This work provides an accurate methodology for extracting the floatinggate gain factory, of CMOS floatinggate inverters with a clockdriven switch for accessing temporarilly to the floatinggate. With the methodology proposed in this paper, the γ factor and other parasitic capacitances coupled to the floatinggate can be easily extracted in a mismatchfree approach. This parameter plays an important role in modern analog and mixedsignal CMOS circuits, since it limits the circuit performance. Theoretical and measured values using two test cells, fabricated in a standard double poly double metal CMOS AMIABN process with 1.2 µm design rules, were compared. The extracted parameters can be incorporated into floatinggate PS pice macromodels for obtaining accurate electrical simulation.
Keywords: FGinverter, neuMOS, floatinggate.
Resumen
En este trabajo se brinda una metodología precisa para la extracción del factor de ganancia γ de la compuerta flotante en inversores CMOS, que constan de un interruptor para acceder temporalmente a la compuerta flotante. Con la metodología propuesta, el factor γ y otras capacitancias parásitas acopladas a la compuerta flotante pueden ser extraídas. Estos parámetros son de mucha importancia, ya que juegan un papel importante en el desempeño de circuitos analógicos y de señal mixta. La comparación entre cálculos teóricos y simulaciones es hecha utilizando dos celdas de prueba fabricadas de tecnología AMI ABN de 1.2 µm, a través de la organización MOSIS. Los parámetros extraídos pueden ser incorporados a macromodelos en PSpice para obtener simulaciones más precisas.
Descriptores: inversor de compuerta flotante, NeuMOS, compuerta flotante.
Introduction
The CMOS floatinggate inverters with multiple inputs have become a useful circuit block in modern analog and mixedsignal circuit design. A CMOS floatinggate inverter is a typical CMOS inverter with two or more input capacitances coupled to the floating gate (FG), which is common to both N and P channel enhancement MOSFET transistors which are connected in the drain mode. The potential induced in the FG can be controlled as a weighted linear sum, in voltagemode, of all input signals. The potential of the FG establishes the onoff state of the CMOS inverter (Shibata et al, 19921993).
Discharging of the FG is commonly required but also, for many applications, it is desirable to precharge the FG to a given bias voltage. Discharging and precharging the FG can be achieved by using an analog switch that connects temporally the FG to an externally applied potential (VRES). By using an external voltage VRES = 0V, the FG can be discharged and the typical UV erasing technique can be avoided (figure 1). This concept has been introduced first in (Kotani et al, 19951998) and was named as clockedcontrolled NeuMOS inverter, but it will be referred as clockedcontrolled FGCMOS inverter.
The FG gain factor γ, determines the maximum input contribution to the FG potential. For n capacitive inputs it is expressed as:
Where CT is the total capacitance including parasitic capacitances. The physical characterization of the FG gain factor γ, also known as the capacitive coupling coefficient, and the parasitic capacitances coupled to the FG, is a fundamental step in the design of high performance FGCMOS based circuits, since the device behavior strongly depends on these values. The strategy followed in this work consists in comparing some features of the transient behavior in the "reset" and "evaluation" periods. One advantage of this approach is that the extraction of the above mentioned parameters can be done to the FG inverter without the use of a "dummy cell" (Mondragón et al, 2000), resulting in an accurate mismatchfree techniques, and whose evaluation will be demonstrated by comparing theoretical and measured results in the next sections.
Clockcontrolled FGCMOS inverter
Electrical charge and potential in the FG using an ideal analog switch
The electrical equivalent circuit for the FG inverter showing the control and relevant parasitic capacitances is shown in figure 2.
According to figure 1, the total charge stored in the FG, QFG is given by:
where Ci, is the capacitance between the FG and the input node i, Vi is the ith input voltage, VDN, VDP, VSN , VSP and VBN , VBP are the drain, source and substrate voltages for the NMOS and PMOS transistors, respectively. From now on, the right side subscripts N and P will denote NMOS and PMOS, respectively. CFDN,, CFDP and CFSN,, CFSP are the overlap capacitances between the FG and the drain or source, respectively. CFBN , and CFBP are the overlap capacitances between the FG and the bulk along the edge of the channel, COXN and COXP are the gate oxide capacitances, CDFPN and CDFPP in figure 2, are the depletion layer capacitances, which can be neglected after the channel begins to form the floating gate (Shibata et al., 1993). Potentials φSN and φSP represent the surface potential of the silicon substrate. Cpoly is the parasitic capacitance between the FG (polysilicon backplate) and the below substrate layer tied to a Vx potential. In this case, for a P substrate Vx = GND. Potential VRFS is the voltage transferred to the FG through the switch. All voltages in (2) are relative to substrate.
It is assumed that no charge injection and no charge leakage occur during device operation. Then, from the charge conservation law on the FG, (2) can be simplified and rearranged to obtain an expression for the potential on the FG, VFG, when the initial net charge is zero, this is given by:
where the potentials at the reset period are represented by (), this is, when the reset switch is closed, and the potentials at the evaluation period represented by (+1), when the switch is open. In (3), Vi(+ 1) represents the ith input voltage during the evaluation period, and Vi() is the ith input voltage applied during the reset period. The remaining potentials terms, coupled to the FG do not contribute with charge in both periods, but their associated capacitances contribute to form CT, which is defined as the sum of all capacitances coupled to the FG as follows.
Potential in the FG using a real analog switch
For practical implementations, a single Nchannel MOSFET can be used in stead of the SW element as shown in figure 2. In figure 3, an equivalent circuit for the FG inverter using a real switch is introduced.
If the access switch transistor (SW) is ni cut off region, a simplest electrical equivalent circuit for the FG potential can be obtained (Ramírez et al., 2004), figure 4, where all the inputs are tied together and form a single input capacitor CIN, CIN = C1+...+Ci+...+Cn. Capacitance COUT represents the sum of CFDP and CFDN. The Cpi capacitor is the ith parasitic capacitance that couples the FG to a DC voltage VDCi.
Here, the ideal diode element models the N+/P parasitic drainbulk junction, associated to the access switch transistor (SW) in cut off and Rleak is an approximation to the nonlinear leakage resistance of this junction.
The input VIN voltage contribution to the FG potential can be obtained through the solution of a simplified circuit (figure 5a).
Where the capacitance CT' is defined as CT' =CT CIN. By conducting a Thevenin reduction to the circuit, the clamping circuit in figure 5b is obtained. For any period ical and continuous voltage signal applied to the circuit, VIN =AIN f1(t+nT) with amplitude AIN and period T, such that T << RleakCT, figure 5c, the FG potential due only to this inputsignal, figure 5d, will be given by:
The same analysis holds for the corresponding contribution on the FG potential as a function of a periodical output signal VOUT=AOUT f2(t+nT), coupled to the FG through COUT, as follows:
For the DC contribution, the following analytical timedomain expression for the FG potential is obtained:
The global expression that models the FG potential will be obtained by summing equations (5), (6) and (7), this is:
During the evaluation period, the terms associated to DC potentials coupled to the FG, vanish for t>>RleakCT. This means that the induced DCcharge on the FG at circuit startup and the resetcharge due to VRES, will be swept out during the evaluation period, after several circuittime constants RleakCT. Therefore, in steadystate, the FG potential will be:
By deriving equation (9) with respect to time, the following expression is obtained
where, γ=CIN/CT is the FG gain factor and γpar= COUT/CT would correspond to a parasitic FG gain factor due to the feedback of the FGMOS inverter's output voltage on the FG.
In reset mode, applying a direct signal to the FG, i.e. a sawtooth, the slope of the inverter transfer characteristic associated to the circuit shown in figure 6a, is given by:
In a similar way, as illustrated in figure 7a, the slope of the transfer characteristic, when the circuit operates in the evaluation period, is given by
Now substituting (11) and (12) in (10), the following relation is obtained:
Where, the slopes AVE and AVR can be easily measured in order to extract the parameters γ and γpar
Extraction methodology
The basic idea that supports the extraction methodology consists in comparing the inverter transient response obtained in the reset period with that obtained during the evaluation period. The extraction methodology is presented next as a sequence of six steps:
Step 1. A measurement during the reset period of AVR is taken around a fixed point in VIN which corresponds to a lowgain slope of the output characteristic (VOUT), (figure 6b).
Step 2. A measurement during the evaluation period of AVE is taken around the same point of step 1, (figure 7b).
Step 3. Parameter γ is calculated using (13). The second term of the right side of this equation is negligible in the lowgain region due to γpar<γ and since AVE is small, then, γ approaches to
Step 4. A measurement during the reset period of AVR is taken at a fixed point VIN near the switchingpoint of the inverter, which corresponds to a highgain slope of the output characteristic, (figure 6b).
Step 5. A measurement in the evaluation period of AVE is taken at the same point of step 4, see figure 7b.
Step 6. From (13), γ is calculated using the values obtained in the steps 3, 4 and 5, by using
Experimental results
Two test cells were fabricated using a doublepoly doublemetal CMOS process with 1.2µm design rules, available through MOSIS services (run: T2AHBJ and T48SAM). The microphotograph of each test cell is shown in figure 8. The first test cell corresponds to the circuit introduced in figure 6a. The schematic diagram for the second test cell is not shown, but is a sixinput FGCMOS inverter.
The test cells were measured using the described methodology presented in section 3. The smallsignal slopes were computed by using a linearfit approximation from data points obtained by means of a digital oscilloscope. Table 1, shows the theoretical and extracted values for γ and γpar using a 100 kHz sawtooth signal with 5V peaktopeak and a 2.5V offset. The period of this signal (T=10µs) is smaller than the intrinsic circuittime constant which normally is in the order of seconds.
Discussion
Although the theoretical capacitance values can be calculated using the process parameters given by the foundry, the physical differences of the input capacitances can lead to an important deviation of γ factor and thus affecting significantly the circuit operating point. As an example, two identical CMOS inverters were simulated through PSpice, one of them with an input capacitance deviation of 5% (figure 9a).
The inverters outputs are shown in figure 9b. The switching operating point (Jacob et al., 1998) of the inverters as shown, is shifted near by 60mV with respect the input voltage Vin , this condition is undesirable for many analog and mixed signal applications since the recent lowvoltage trends requires high accuracy. The methodology presented in this work focuses on CMOS floatinggate circuits with a clockdriven switch at the FG, and represents a good choice when the γ factor must be determined experimentally for high accuracy requirements.
Acknowledgements
Mexico State Autonomous University (CU UAEMEcatepec), Interdisciplinary Professional School of Engineering and Advanced Technologies (UPIITAIPN) and National Institute for Astrophysics, Optics and Electronics, INAOE.
References
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About the authors
Jesús Ezequiel MolinarSolis. Was born in Chihuahua, Mexico, in 1976. He received the electronics engineering degree from the Technological Institute from Ciudad Guzman (ITCG), Jalisco, in 1999. He obtained the M.Sc. and Ph.D. degrees in electrical engineering at the Center for Research and Advanced Studies (CINVESTAVIPN), Mexico City, in 2002 and 2006 respectively. He is currently working as a Titular Professor with the Mexico State Autonomous University (UAEM) at Ecatepec, Estado de Mexico, his research interests are related to analog circuits, neural networks and vision chips.
Victor Hugo PoncePonce. Received the B. Tech. degree in electronics engineering from the Superior School of Mechanical and Electrical Engineering (ESIME) of the National Polytechnic Institute (IPN) of Mexico, in 1993, and the M. of Sc. and Ph.D. degrees in electrical engineering from Center for Research and Advanced Studies (CINVESTAVIPN) at Mexico City, in1994 and 2005, respectively. He is currently working as Professor at the Computer Research Centre CICIPN. His research interests include CMOS design circuits and vision sensors.
Rodolfo Zola GarciaLozano. Was born in Mexico City, Mexico in 1973. He received the electronics engineering degree from Technologic of Advanced Studies from Ecatepec (TESE), Mexico in 1996. He obtained the Ph.D degree in Electrical Engineering at the Center of Research and Advanced Studies (CINVESTAVIPN), Mexico City, in 2005. He is currently working as a Titular Professor with the Mexico State Autonomous University (UAEM) at Ecatepec, Estado de Mexico. His research interests are related to electronics circuits and thin film devices application.
Alejandro DíazSánchez. Received the B.E. from the Madero Technical Institute and the M.Sc. from the National Institute for Astrophysics, Optics and Electronics, both in México, and the Ph.D. in Electrical Engineering from New Mexico State University at Las Cruces, NM. He is actually working as Full Professor at the National Institute for Astrophysics, Optics and Electronics, in Tonantzintla, Mexico. His research concerns analog and digital integrated circuits, high performance computer architectures and signal processing.
José Miguel RochaPérez. Was born in Huixcolotla, Puebla, México. He received the B.S. degree in electronics from the Universidad Autónoma de Puebla, Puebla, México in 1986 and the M.Sc. and Ph.D. degrees from the Instituto Nacional de Astrofísica Óptica y Electrónica (INAOE), Puebla, in 1991 and 1999, respectively. He was a Visiting Researcher in the Department of Electrical Engineering, Texas A&M University, College Station in 2002. Currently, he is working at INAOE in the Electronics Department and his current research interests are on the design of integrated circuits for communications.