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Computación y Sistemas

versión impresa ISSN 1405-5546

Comp. y Sist. vol.19 no.3 México jul./sep. 2015

 

Artículos

 

HW/SW Co-Design of a Specific Accelerator for Robotic Computer Vision

 

Adrián Pedroza de la Crúz1, Miguel Ángel Carrazco Díaz1, Susana Ortega Cisneros1, Juan José Raygoza Panduro2, Jorge Rivera Domínguez3, Federico Sandoval Ibarra1

 

1 Instituto Politécnico Nacional, CINVESTAV Jalisco, México. apedroza@gdl.cinvestav.mx, mcarrazco@gdl.cinvestav.mx, sortega@gdl.cinvestav.mx, sandoval@gdl.cinvestav.mx

2 University of Guadalajara, CUCEI, Jalisco, México. juan.raygoza@cucei.udg.mx

3 Instituto Politécnico Nacional, commissioned as a CONACyT professorship to CINVESTAV, Jalisco, México. riveraj@gdl.cinvestav.mx

Corresponding author is Adrián Pedroza de la Crúz.

 

Article received on 08/12/2014.
Accepted on 29/04/2015.

 

Abstract

This paper presents an image processing application focused on robotic computer vision. The co-design is divided into three main parts: a hardware accelerator, a PCIe® based framework for HW/SW link, and application software. The implemented accelerator performs preprocessing for facial recognition in order to reduce the workload in the main system processor. The hardware layer is implemented in Altera FPGAs, while the project software layer provides a device driver for Linux to link the user application with the coprocessor. The user application controls the data transfer between the operating system and the device driver. The platform allows rapid prototyping of accelerators, taking advantage of the duality of a programmable hardware and a general purpose processor connected through a PCIe® link. The proposed architecture enables co-design of various image processing algorithms. In this case, the results of the design of an accelerator that performs histogram equalization for contrast correction of color images are presented.

Keywords: Accelerator for computer vision, design automation, field-programmable gate array (FPGA), hardware accelerator, hardware design, high performance computing, Linux driver, PCIe framework, Verilog.

 

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Acknowledgment

The authors are grateful for the financial support provided in part by CONACYT (National Council of Science and Technology) as a doctoral fellowship grant.

 

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