SciELO - Scientific Electronic Library Online

 
vol.19 issue2Segmentation Strategies to Face Morphology Challenges in Brazilian-Portuguese/English Statistical Machine Translation and Its Integration in Cross-Language Information RetrievalIdentification of Harmonic Sources in Electrical Power Systems Using State Estimation with Measurement Error author indexsubject indexsearch form
Home Pagealphabetic serial listing  

Services on Demand

Journal

Article

Indicators

Related links

  • Have no similar articlesSimilars in SciELO

Share


Computación y Sistemas

Print version ISSN 1405-5546

Comp. y Sist. vol.19 n.2 México Apr./Jun. 2015

http://dx.doi.org/10.13053/CyS-19-2-1941 

Artículos

 

Design of a General Purpose 8-bit RISC Processor for Computer Architecture Learning

 

Antonio Hernández Zavala1, Oscar Camacho Nieto3, Jorge A. Huerta Ruelas1, Arodí R. Carvallo Domínguez2

 

1 Instituto Politécnico Nacional, Centro de Investigación en Ciencia Aplicada y Tecnología Avanzada, Mechatronics Department, Querétaro, México. anhernandezz@ipn.mx, jhuertar@ipn.mx

2 Instituto Politécnico Nacional, Unidad Profesional Interdisciplinaria en Ingeniería y Tecnologías Avanzadas, Engineering Department, Mexico City, México. acarvallo@ipn.mx

3 Instituto Politécnico Nacional, Centro de Innovación y Desarrollo Tecnológico en Cómputo, Mexico City, México. ocamacho@ipn.mx

Corresponding author is Antonio Hernández Zavala.

 

Article received on 27/11/2014.
Accepted on 15/01/2015.

 

Abstract

Computers are becoming indispensable for manipulating most everyday consumer products, ranging from communications and domestic electronics to industrial processes monitoring and control. High performance computer design is not only subject to the technology used for its implementation, it is also a matter of efficient training. The skills that must prevail in a good computer designer come from the type of courses taken and the tools employed during them. This work shows the design of an 8-bit RISC soft-core processor dedicated to a complete understanding of computer architecture. We consider this Processor an effective hands-on training solution for the comprehension of a computer from its lowest level up to testing.

Keywords: Computer architecture, digital design, digital logic, microprocessor, programmable logic devices, training system.

 

DESCARGAR ARTÍCULO EN FORMATO PDF

 

Acknowledgements

Authors would like to thank Instituto Politécnico Nacional and CONACYT who funded this work.

 

References

1. Berkeley, E.C. & Jensen, R.A. (1950). World's Smallest Electric Brain. Radio-Electronics, Oct. 1950.         [ Links ]

2. Illinois State University (2000). Little Man Computer. http://www.acs.ilstu.edu/faculty/javila/lmc/        [ Links ]

3. Bell Laboratories Record (1969). Cardboard "Computer" Helps Students, 216.         [ Links ]

4. Yutaka, S. Paper Processor. Available: https://sites.google.com/site/kotukotuzimiti/        [ Links ]

5. Langdon, G.G. (1982). Computer Design. Computeach press, California.         [ Links ]

6. Hennessy, J.L. & Patterson, D.A. (1990). Computer Architecture: A quantitative Approach. Morgan Kaufmann San Mateo CA.         [ Links ]

7. El Aarag, H. (2009). A complete design of a RISC processor for pedagogical purposes. Journal of Computing Sciences in Colleges, Vol. 25, No.2, pp. 205-213.         [ Links ]

8. Rodríguez, B.J. (1994). A minimal TTL processor for architecture exploration. Proceedings of the 1994 ACM symposium on applied computing, pp. 338-340.         [ Links ]

9. Massachussetts Institute of Technology. MIT 6.004 Beta Architecture Information. Available: http://6004.csail.mit.edu/Spring98/Beta.         [ Links ]

10. Verplaetse, P. & Campenhout, J. (1999). ESCAPE: Environment for the Simulation of Computer Architecture for the Purpose of Education. IEEE Technical Committee on Computer Architecture Newsletter, pp. 57-59.         [ Links ]

11. Djordjevic, J., Milenkovic, A., & Grbanovic, N. (2000). An Integrated Environment for Teaching Computer Architecture. IEEE Micro, Vol. 20, No. 3, pp. 66-74.         [ Links ]

12. Wainer, G., Daicz, S., De Simoni, L., & Wassermann, D. (2001). Using the Alfa-1 simulated processor for educational purposes. Journal on Educational Resources in Computing, Vol. 1, No.4, pp. 111-151.         [ Links ]

13. Martins, C.A., Correa, J.B., Goes, L.F., Ramos, L.E., & Medeiros, T.H. (2002). A new learning method of microprocessor architecture. Frontiers in Education, 3, S1F16-S1F21.         [ Links ]

14. Pizzutilo, S. & Tangorra, F. (2003). A learning environment to teach computer architecture. Proceedings of the WSEAS International Conference on Information Science and Application, pp. 770-776.         [ Links ]

15. Jaumain, M., Osee, M., Richard, A., Vander Biest, A., & Mathys, P. (2007). Educational simulation of the RISC processor. International Conference on Engineering Education.         [ Links ]

16. García, M.I., Rodríguez, S., Pérez A., & García, A. (2009). p88110: A Graphical Simulator for Computer Architecture and Organization Courses. IEEE Transactions on Education, Vol. 52, No. 2, pp. 248-256. DOI: 10.1109/TE.2008.927690        [ Links ]

17. Hsiao-Ping, Holmes, N.D., Bakshi, S., & Gajski, D.D. (1993). Top-down modeling of RISC processors in VHDL. Design Automation Conference 1993 with EURO-VHDL, pp. 454-459.         [ Links ]

18. Li, Y. & Chu, W. (1996). Using FPGA for computer architecture/organization education. Proceedings of the 1996 workshop on Computer architecture education, pp. 31 -35.         [ Links ]

19. Gray, J. (2000). Hands-on computer architecture: teaching processor and integrated systems design with FPGAs. Proceedings of the workshop on Computer architecture education, article 17. DOI: 10.1145/1275240.1275262        [ Links ]

20. Becvar, M., Pluhacek, A., & Danecek, J. (2003). DOP: a CPU core for teaching basics of computer architecture. Workshop on Computer architecture education, article 4.

21. Muñoz, A.S., & Rodríguez-Morcillo, J.D. (2008). Microprocesador RISC sintetizable en FPGA para fines docentes. VIII Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica, España.         [ Links ]

22. Mandalidis, D., Kenterlis, P., & Ellinas, J. (2008). A computer architecture educational system based on a 32-bit RISC processor. International Review on computers and Software, pp. 114-119.

23. Wadhankar, V.R. & Tehre, V. (2012). A FPGA Implementation of a RISC Processor for Computer Architecture. Proceedings on National Conference on Innovative Paradigms in Engineering and Technology, Vol. 1, pp. 24-28.         [ Links ]

24. Calazans, N.L.V., & Moraes, F.G. (2001). Integrating the teaching of computer organization and architecture with digital hardware design early in undergraduate courses. IEEE Transactions on Education, Vol. 44, No. 2, pp. 109-119. DOI: 10.1109/13.925805        [ Links ]

25. Becvar, M., Pluhacek A., & Danecek, J. (2003). DOP: a CPU core for teaching basics of computer architecture. Proceedings of the workshop on Computer architecture education, article 4. DOI: 10.1145/1275521.1275527        [ Links ]

26. Angelov, V. & Lindenstruth, V. (2009). The educational processor Sweet-16. International Conference on Field Programmable Logic and Applications, pp. 555-559. DOI: 10.1109/FPL.2009.5272412        [ Links ]

27. Presa, J.L. & Calle, E.P. (2011). MMP16 a 16-bit Didactic Micro-Programmed Micro-Processor. International Conference on Computer Research and Development, Vol. 1, pp. 61-65. DOI: 10.1109/ICCRD.2011.5763974        [ Links ]

28. Oztekin, H., Temurtas, F., & Gulbag, A. (2011). BZK.SAU.FPGA10.0: Microprocessor architecture design on reconfigurable hardware as an educational tool. IEEE Symposium on Computers & Informatics, pp. 385-389. DOI: 10.1109/ISCI.2011.5958946        [ Links ]

29. Pereira, M.C., Viera, P.V., Raabe, A.L., & Zeferino, C.A. (2012). A basic processor for teaching digital circuits and systems design with FPGA. Southern Conference on Programmable Logic, pp. 1-6. DOI: 10.1109/SPL.2012.6211804        [ Links ]

30. Hernández Zavala, A., Avante Reyes, J., Duarte Reynoso, Q., & Valencia Pesqueira, J.D. (2011). RISC-Based Architecture for Computer Hardware Introduction. International Conference on Computer Research and Development, pp. 17-21.         [ Links ]

31. Pattersson, D.A. & Hennessy, J.L. (1998). Computer Organization and Design, the hardware/software interface (2nd ed.). Morgan Kaufmann San Francisco CA.         [ Links ]

32. Tocci, R.J., Widmer, N.S., & Moss, G.L. (2007). Sistemas Digitales, Principios y aplicaciones (10th ed.), Pearson, México.         [ Links ]

33. Stallings, W. (1994). Organización y Arquitectura de Computadoras (7th ed.). Pearson, México.         [ Links ]

34. Mano, M. (1994). Arquitectura de computadoras (3th ed.). Pearson, México.         [ Links ]

35. Jaramillo Gómez, J.A., Guzmán Domínguez, I., & Molina Lozano, H. (2011). VHDL. Guia de Estilo y Prácticas de Laboratorio de Circuitos Lógicos. Instituto Politécnico Nacional, México.         [ Links ]

Creative Commons License All the contents of this journal, except where otherwise noted, is licensed under a Creative Commons Attribution License