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Computación y Sistemas

Print version ISSN 1405-5546

Comp. y Sist. vol.14 n.3 México Jan./Mar. 2011

 

Artículos

 

A Low–Complexity current–mode WTA circuit based on CMOS Quasi–FG Inverters

 

Circuito WTA en modo de corriente y baja complejidad, basado en inversores Quasi–FG en CMOS

 

Jesús Ezequiel Molinar Solís,1 Luis Abraham Sánchez Gaspariano,2 Rodolfo Zolá García Lozano1, Víctor Ponce Ponce3, Juan J. Ocampo Hidalgo4, Herón Molina Lozano3 and Alejandro Díaz Sánchez2

 

1 Universidad Autónoma del Estado de México UAEM, Jose Revueltas 17, Tierra Blanca, 55020, Ecatepec, +52 (55) 57873626, MEXICO. Email: jemolinars@uaemex.mx

2 National Institute of Astrophysics, Optics and Electronics, INAOE Luis E. Erro 1, Tonantzintla, Puebla, +52 (222) 2663100, MEXICO.

3 Centro de Investigación en Computación del IPN, Av. Juan de Dios Batiz s/n, Col. Nueva Industrial Vallejo, C.P. 07738, México D.F. +52 55 57296000

4 Universidad Autónoma Metropolitana, UAM, Unidad Azcapotzalco, Av. San Pablo No. 180, Col. Reynosa Tamaulipas, C.P. 02200, México D.F. +52 55 43189000

 

Article received on February 04, 2009
Accepted on November 09, 2009

 

Abstract

In this paper, a low–complexity current–mode Winner–Take–All circuit (WTA) of O (n) complexity with logical outputs is presented. The proposed approach employs a Quasi–FG Inverter as the key element for current integration and the computing of the winning cell. The design was implemented in a double–poly, three metal layers, 0.5µm CMOS technology. The circuit exhibits a good accuracy–speed tradeoff when compared to other reported WTA architectures.

Keywords. Winner–take–all, neural networks, analog circuits.

 

Resumen

En este artículo, se presenta un circuito "ganador toma todo" (WTA) de baja complejidad en modo de corriente con salidas digitales. La propuesta se basa en el uso de un inversor que utiliza la técnica de Quasi–FG, el cual, realiza una integración de corriente y el cómputo de la celda ganadora. El diseño fue implementado usando una tecnología de doble polisilicio y tres capas de metal para interconexión en tecnología CMOS de 0.5µm. El circuito presenta buena precisión y velocidad en comparación con otras arquitecturas WTA existentes.

Palabras clave: Ganador toma todo, redes neuronales, circuitos analógicos.

 

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References

1. Chieng–Cheng Yu, Yun–Chiang Tang & Bin–Da Liu (2003). Design of High Performance CMOS current–mode Winner–Take–All Circuit, 5th International Conference on ASIC, Beijing, China, 1, 568 – 572.         [ Links ]

2. Cilingiroglu U., Dake L. E. (2002). Rank–Order Filter Design with a Sampled–Analog Multiple–Winners–Take–All Core, IEEE Journal of Solid State Circuits, 37(8), 978–984.         [ Links ]

3. DeWeerth S. P. & Morris T. G. (1995), CMOS Current Mode Winner Take All Circuit with Distributed Hysteresis, Electronics Letters, 31(13), 1051–1053.         [ Links ]

4. Fish A., Milrud V. & Yadid–Pecht O. (2005). High Speed and High–Precision Current Winner–Take–All Circuit, IEEE Transactions on Circuits and Systems II, 52(3), 131–135.         [ Links ]

5. Lazzaro J., Ryckebusch S., Mahowald M. A. & Mead C. A. (1989), Winner–Take–All Networks of O(n) Complexity, Advances in Neural Signal Processing Systems 1 (703–711). San Francisco, CA: Morgan Kaufmann Publishers Inc.         [ Links ]

6. Li Zhijian, Shi Bingxue & Lu Wei, (1998). Current–Mode Hamming Neural Network, U.S. Patent 5,720,004.         [ Links ]

7. Liu S., Chen P., Chen C. & Hwu J. (1997), Analog Maximum, Median and Minimum Circuit, IEEE International Symposium of Circuits and Systems, HongKong, China, 257–260.         [ Links ]

8. Massari N., & Gottardi M. (2006), Low power WTA circuit for Optical Position Detector, Electronics Letters, 42(24), 1373–1374.         [ Links ]

9. Molinar–Solis J. E., Garcia–Lozano R. Z. Padilla–Cantoya I. Diaz–Sanchez A. & Rocha–Perez J. M. (2009). On the Characterization of the Trapped Charge in FG–CMOS Inverters, Analog Integrated Circuits and Signal Processing, 61(2), 191–198.         [ Links ]

10. Yamashita T., T. Shibata & T. Ohmi, (1993). Neuron MOS Winner–Take–All Circuit and its Application to Associative Memory, IEEE International Solid–State Circuit Conference, 40th ISSCC, San Francisco, CA, USA, 236–237.         [ Links ]

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