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Computación y Sistemas

versión impresa ISSN 1405-5546

Comp. y Sist. vol.10 no.2 México oct./dic. 2006

 

Parallel Hardware/Software Architecture for the BWT and LZ77 Lossless Data Compression Algorithms

 

Arquitectura Hardware/Software Paralela para los Algoritmos de Compresión de Datos sin Pérdida BWT y LZ77

 

Virgilio Zuñiga Grajeda, Claudia Feregrino Uribe and Rene Cumplido Parra

 

National Institute for Astrophysics, Optics and Electronics Luis Enrique Erro No. 1. Tonantzintla, Puebla, Mexico. Postal Code: 72840 virgilio@inaoep.mx ; cferegrino@inaoep.mx ; rcumplido@inaoep.mx

 

Article received on july 25, 2006
Accepted on october 2, 2006

 

Abstract.

Nowadays, the use of digital communication systems has increased in such a way that network bandwidth is affected. This problem can be solved by implementing data compression algorithms in communication devices to reduce the amount of data to be transmitted. However, the design of large hardware data compression models implies to consider an efficient use of the silicon area. This work proposes the conjunction of two different hardware lossless data compression approaches which share common hardware elements. The project also involves the design of a hardware/software architecture to exploit parallelism increasing execution speed while keeping flexibility. A custom coprocessor unit executes the compute–intense tasks of the Burrows–Wheeler Transform and the Lempel–Ziv lossless data compression schemes. This coprocessor unit is controlled by a SPARC V8 compatible general purpose microprocessor called LEON2.

Keywords: Data compression, Burrows–Wheeler Transform, Lempel–Ziv, Coprocessor, LEON2.

 

Resumen.

Hoy en día, el uso de sistemas de comunicación digitales ha aumentado de tal forma que el ancho de banda en las redes resulta afectado. Este problema puede solucionarse implementando algoritmos de compresión de datos en dispositivos de comunicación reduciendo la cantidad de datos a transmitir. Sin embargo, el diseño de modelos complejos de compresión de datos en hardware implica considerar el uso eficiente de la superficie de silicio. Este trabajo propone la combinación de dos esquemas diferentes de compresión de datos sin pérdida que compartan elementos comunes. Este proyecto también trata el diseño de una arquitectura hardware/software que explote el paralelismo e incremente la velocidad de ejecución manteniendo su flexibilidad. Un coprocesador ejecuta las tareas computacionalmente intensas de los esquemas de compresión Burrows–Wheeler Transform y Lempel–Ziv. El coprocesador es controlado por un microprocesador de propósito general compatible con la arquitectura SPARC V8 llamado LEON2.

Palabras clave: Compresión de Datos, Transformada de Burrows–Wheeler, Lempel–Ziv, Coprocesador, LEON2.

 

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Acknowledgments

The authors acknowledge the financial support from the Mexican National Council for Science and Technology (CONACyT), grant number 181512.

 

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