1.Introduction

The Data Processing Electronics Interface described here is designed to acquire and process 10-bit signals for avalanche photodiodes (APDs) [¹] with a metal resistor semiconductor and a Hamamatsu R6095 photomultiplier (PMT) [²] integrated in a plastic scintillator particle detector. The interface’s architecture contains several blocks to avoid typical perturbations due to temperature variation in electronics, detectors, and induced noise. The data processor system is able to perform a continuous read out, identify a valid signal pulse, reject glitches, and compress the data without any loss of information. The signals are compressed in the data compression block which removes all data below a predefined voltage threshold and identifies a pulse when three consecutive data values are over the threshold. Each pulse is tagged with a time stamp, number of samples, and event number for reconstruction purposes. All pulses are formatted and stored in a multi-event buffer with a bandwidth of 200 Mbytes/s. In continuous mode, the maximum input data rate is 40 MHz, where all the signals coming from the analog-to-digital converts (ADCs) are stored in a dual port memory. The maximum read frequency for the dual port memory is 300 MHz. The interface can generate a calibration signal that allows to detect errors in any of the blocks. The system has been tested with particle detectors based on APDs and photomultipliers (PMTs) triggered with atmospheric muons. The interface is designed to process large data volumes without any loss of information. The output signal is the same regardless a PMT or an APD is connected to the input of the interface. The maximum rate expected for a single channel is about 260 bits/event with up to eight channels allowed in a single FPGA interface.

2. Materials and methods

A front-end electronic card (FEE) is designed to digitize the signals from the PMTs and APDs. This FEE, in Fig. 1, is composed by a charge preamplifier, a 4^th order shaping amplifier and a 10 bit 40 MHz ADC.

Figure 1 Front-end card to read out the APD and PMT detector signals. 

Up to eight FEE cards can work in parallel connected to a single interface card. Since the output data are 10-bit wide, all of the FEE signals would require 80 inputs and 8 dedicated output from the field-programmable gate arrays (FPGA), which are the maximum number of I/O’s on it. The 8 dedicated outputs are required to distribute the clock signals for each FEE to synchronize the operation and data transfer without jitter issues. The data processing interface card we designed is a 9.5×9 cm², 8 layer PCB. The card is equipped in the top side with four header connectors for up to 185 I/O, 3 power supply connectors, one 100 MHz SMD oscillator, one I2 C configurable oscillator, three power regulators, a configuration memory, and a microcontroller for the USB interface control. The system is based on an ALTERA Cyclone V FPGA (5CEBA2F23C8N). An 8 layer PCB (see Fig. 2] was specifically designed to mount the FPGA, the components to process the digitized signals and a microcontroller to drive the USB interface for data transfer.

Figure 2 Interface Board. The FPGA is at the center and the microcontroller is on the right. 

The firmware of the interface consists of the five main blocks shown in Fig. 3: a) the Ring Buffer is a dual port memory [³] of 8192×10 bits with a write frequency of 40 MHz and a read frequency of 80 MHz; b) the Pulse Finder is a pulse scanner, it is used to identify a valid pulse and reject the signals without valid information; c) the Data Format receives a valid pulse and adds a time stamp, data length and data number. This block also generates an empty event to preserve time continuity whenever no pulse is processed for a long time; d) the Multi-Event Buffer is based on a first-in first-out (FIFO) [⁴] memory where the pulses processed by all channels are temporarily stored before they are sent to an external permanent storage system, the read-out frequency is determined by the FIFO memory, the maximum transfer speed is 200 Mbytes/s; e) the Main Control synchronizes the operation of the blocks, receives the configuration parameters, and distributes the sequences to start and stop the data processing.

Figure 3 Schematic diagram of the Interface Board firmware. There are three clock domains controlled by an internal Phaselocked loop (PLL) in the FPGA. All the blocks run in a clock domain two times faster than the writing frequency of the Ring Buffer to assure there is always free space for continuous data acquisition. 

2.3.Event format

The Data Format block constructs the internal data format for valid pulses and empty events. The data format for a valid pulse is composed of a start of event value that identifies each pulse, the channel number, a time stamp with respect to the previous pulse, the payload, the data length, and the number of data. For an empty event, the data format is composed of a start of data value, the channel number, time stamp, the data length, and the data number. The empty events are inclu-ded only if the maximum waiting time for a valid pulse has elapsed; the purpose of this is to preserve time continuity and to identify the exact time when a muon is detected with respect to the internal clock of the FPGA. Figure 4 shows the internal data format for empty and valid events.

Figure 4 On the left, the data packet for a valid pulse and, on the right, the data packet for an empty event. 

3.Results

Digitized signals from cosmic rays in plastic scintillating detectors [⁶] are used as data source to test the interface; these detectors are the same used for the cosmic ray detector (ACORDE) [⁷]. The digitized signals come from a 10 bit 40 MHz ADC. The analog to digital conversion is activated by the Main Control Block. The maximum input signal rate that the system can handle is 10 KHz for both PMTs and APDs. The data processing interface is able to acquire digital signals through the implementation of the following functions in the FPGA’s firmware: clock distribution, configuration for the data acquisition, data formatting, and transfer to an external storage system. The system can also generate a test signal for calibration purposes. The signals from the ADC are 650 ns wide and are sampled at a rate of 20 MHz. Figure 5 shows the user interface of the acquisition system.

Figure 5 Data acquisition user interface for system configuration and control. 

The connection button between the interface and the data acquisition system (DAQ) system is indicated with the number 1 in the figure, number 2 indicates the discriminator voltage input field for all the acquisition channels, number 3 is the button to enable the data storage in a specific file, and number 4 is the graphic area to display all the data from the FEE cards.

Besides processing and storing all the digitized signals, the maximum value of each signal is also measured and recorded. Figures 6 and 7 show the amplitude distribution for APD and PMT signals, respectively. For APDs the threshold was set to 4 ADC counts, the duration of the test was 57 minutes and the optimum bias Voltage 35.5 V. For the PMT, the discrimination threshold was 4 ADC counts, the duration of the test was 70 minutes and the optimum operational Voltage was 700 V.

Figure 6 Amplitude distribution of the APD signals. 

Figure 7 Amplitude distribution of the PMT signals. 

A test signal of amplitude 714 ADC counts is stored in the firmware. One hundred thousand events with this test signal were injected to the FPGA during a period of 14 hours. The amplitude distribution of these events is shown in Fig. 8 where it is clear that the system does not register events of an incorrect amplitude.

Figure 8 Reconstruction of the maximum value for the internal test signal in the firmware. 

4.Discussion

We can observe that the threshold level was the same for the PMT and the APD. It is usually expected for APDs to be noisier than PMTs; nevertheless, the FEE cards are able to drive the signals from both detectors. When an interruption occurs in the data transfer, the processing interface pauses the operation, only to be resumed when the resources become ready. During this pause period, the processing interface does not interrupt the data acquisition from the ADCs preventing any data loss. In addition, if the USB data transfer is stopped, the interface is capable of taking data for 1 more minute, since the Ring Buffer is able to write data even if the reading part is paused. Finally, the power consumption of the card in standby mode is 100 mA while for each active channel the card consumes 80 mA. Only one 5 V symmetrical power supply is needed to power the system.

5.Conclusions

The FPGA based Processing Interface we designed and built was successfully used to read-out, discriminate, digitize, and transfer signals produced by PMTs and APDs coupled to scintillating plastic detectors. This board is the first prototype based on a FPGA for application in cosmic ray and high energy physics. This interface is an excellent, easy-to-use option for scintillation detectors characterization. Its reduced size makes it ideal for applications where the space and access to the detector area are restricted. The Processing Interface is a novel way for reading out and store data from plastic scintillator based detectors. It is also well suited to test and verify the correct performance of a specific section in a multichannel or single channel detectors. The Pulse Finder module included in the firmware makes an external trigger detector unnecessary. A limitation of this prototype is that only eight channels were implemented for multichannel applications though this is clearly a drawback that can be overcome.