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Journal of applied research and technology

On-line version ISSN 2448-6736Print version ISSN 1665-6423

Abstract

PEDROZA DE LA CRUZ, Adrian et al. Characterization and synthesis of a 32-bit asynchronous microprocessor in synchronous reconfigurable devices. J. appl. res. technol [online]. 2015, vol.13, n.5, pp.483-497. ISSN 2448-6736.  http://dx.doi.org/10.1016/j.jart.2015.10.004.

This paper presents the design, implementation, and experimental results of 32-bit asynchronous microprocessor developed in a synchronous reconfigurable device (FPGA), taking advantage of a hard macro. It has support for floating point operations, such as addition, subtraction, and multiplication, and is based on the IEEE 754-2008 standard with 32-bit simple precision. This work describes the different blocks of the microprocessors as delay modules, needed to implement a Self-Timed (ST) protocol in a synchronous system, and the operational analysis of the asynchronous central unit, according to the developed occupations and speeds. The ST control is based on a micropipeline used as a centralized generator of activation signals that permit the performance of the operations in the microprocessor without the need of a global clock. This work compares the asynchronous microprocessor with a synchronous version. The parameters evaluated are power consumption, area, and speed. Both circuits were designed and implemented in an FPGA Virtex 5. The performance obtained was 4 MIPS for the asynchronous microprocessor against 1.6 MIPS for the synchronous.

Keywords : Asynchronous; Microprocessor; Floating point; FPGA delay macro; Real time.

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