Appendix

Requirements

The VLSI design process with Alliance free CAD tools in education institutions has just a few requirements: an educational course involved in this research area, and minimum hardware and software for its implementation.

First, a VLSI design course covering the basics of electronics and computer science is needed. The background on CMOS devices and manufacturing technology, CMOS inverters and gates, propagation delay, noise margins, and power dissipation, sequential circuits, arithmetic, memories and design methodologies is necessary for understanding, designing, and optimizing digital circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability.

A laboratory with access to computers or workstations is required to design VLSI chips. Alliance VLSI CAD Systems runs over Unix/Linux platforms, from i386 based microcomputers to SparcStations and DecS-tations. The software is registered under the GNU General Public License (GPL), so binaries, source code, and cells libraries are freely distributed. The packages are avalaible online from RedHat Entreprise Linux 6 (RHEL6) and clones (Scientific Linux 6, CentOS 6), Fedora and Ubuntu LTS distributions (LIP6, 2014).

Alliance VLSI CAD Systems provides some process independence in order to allow the designers to easily port their design from one technology process to another, this makes the design of circuits independent of the technology used in their fabrication step.

Alliance CAD set tools

The following tools are used during the synthesis of VLSI digital circuits, for a detailed description see (Lam, 2004) and (Silva et al, 2006).

VASY (VHDL Analyzer for Synthesis). Converts a file written in VHDL VASY subset of the subset of VHDL Alliance.

BOOM (Boolean Minimization). Performs Boolean minimization on the incoming file written in the subset of VHDL Alliance. It is used in the first step of the synthesis process. Optimizes a behavioral description using reduced ordered binary decision diagram for the representation of logic functions.

BOOG (Binding and Optimizing On Gates). Boog is a mapper from a behavioral description into a library of standard cells as SXLIB. It is the second step of logic synthesis. Implements the input file, written in VHDL subset Alliance as a structural VHDL file where all entities used are contained in the specified cell library. The output file format is in VHDL structural Alliance.

LOON (Local Optimizations of Nets). Introduces some buffers to improve the current drive of some cells, but without modifying the original logic function. Both the input file and the output are written in VHDL structural Alliance. It is a CAD tool to remove problems and optimize FANOUT delay times, generating outputs with improved times.

ASIMUT (A SIMUlation Tool for hardware description). Behavioral and structural file format could be the input file for validate digital designs, attached to the subset of VHDL Alliance. But its most important use is to compare the input file against a test premade.

Place & Route

OCP (automatic tool for standard cell placement). Receives a structural VHDL file where all instantiated entities correspond to the previously indicated cell library.

OCP places the plane of each cell layout instantiated on a coordinate plane representing the surface of the chip. The output file does not yet contain information of interconnections but tries to place the cells subsequently interconnect as close as possible.

NERO (NEgotiating ROuter). This tool receives two files: one with extension .ap (generated by OCP) containing the cells positioned in the plane of the chip, and other with the .vst file (generated by LOON) containing the interconnections between the instantiated cells. Generates an .ap file containing cell layouts well positioned and the metal interconnections. The output file is the full layout in symbolic units.

COUGAR (Hierarchical Netlist Extractor). This tool is applied on the symbolic Layout file (extension .ap) produced by Nero Cougar and makes an extracting structural file extension (logical alliance) that subsequently was compared with the structural .vst produced by LOON.

LVX (Logical Versus extracted net-list comparator). Tool for comparing structural .vst and .al format files.

S2R. Tool to convert units in symbolic layout (.ap extension) to a layout in real units (.cif file extension). The CIF file layout in real units is to be sent to the manufacturer for construction.